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Siddharth Garg

Assistant Professor

    20042020

    Research output per year

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    Research Output

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    Conference contribution

    3D-GCP: an analytical model for the impact of process variations on the critical path delay distribution of 3D ICs

    Garg, S. & Marculescu, D., 2009, Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. p. 147-155 9 p. 4810285. (Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    A Concentration of Measure Approach to Database De-anonymization

    Shirani, F., Garg, S. & Erkip, E., Jul 2019, 2019 IEEE International Symposium on Information Theory, ISIT 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 2748-2752 5 p. 8849392. (IEEE International Symposium on Information Theory - Proceedings; vol. 2019-July).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Adaptive Adversarial Videos on Roadside Billboards: Dynamically Modifying Trajectories of Autonomous Vehicles

    Patel, N., Krishnamurthy, P., Garg, S. & Khorrami, F., Nov 2019, 2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2019. Institute of Electrical and Electronics Engineers Inc., p. 5916-5921 6 p. 8968267. (IEEE International Conference on Intelligent Robots and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms

    Ravishankar, C., Ananthanarayanan, S., Garg, S. & Kennings, A., 2012, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 617-624 8 p. 6187557. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Analysis of energy-and SoC-neutral contracts for frequency regulation with energy storage

    Fooladivanda, D., Rosenberg, C. & Garg, S., Mar 17 2016, 2015 IEEE International Conference on Smart Grid Communications, SmartGridComm 2015. Institute of Electrical and Electronics Engineers Inc., p. 743-749 7 p. 7436390. (2015 IEEE International Conference on Smart Grid Communications, SmartGridComm 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator

    Zhang, J., Gu, T., Basu, K. & Garg, S., May 29 2018, Proceedings - 2018 IEEE 36th VLSI Test Symposium, VTS 2018. IEEE Computer Society, p. 1-6 6 p. (Proceedings of the IEEE VLSI Test Symposium; vol. 2018-April).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    An analysis of energy storage and regulation

    Fooladivanda, D., Rosenberg, C. & Garg, S., Jan 12 2015, 2014 IEEE International Conference on Smart Grid Communications, SmartGridComm 2014. Institute of Electrical and Electronics Engineers Inc., p. 91-96 6 p. 7007628. (2014 IEEE International Conference on Smart Grid Communications, SmartGridComm 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    An information theoretic framework for active de-anonymization in social networks based on group memberships

    Shirani, F., Garg, S. & Erkip, E., Jan 17 2018, 55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017. Institute of Electrical and Electronics Engineers Inc., p. 470-477 8 p. (55th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2017; vol. 2018-January).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    BandiTS: Dynamic timing speculation using multi-armed bandit based optimization

    Zhang, J. J. & Garg, S., May 11 2017, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., p. 922-925 4 p. 7927121. (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Can flexible, domain specific programmable logic prevent IP theft?

    Cui, X., Wu, K., Garg, S. & Karri, R., Oct 25 2016, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016. Institute of Electrical and Electronics Engineers Inc., p. 153-157 5 p. 7684088. (2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors

    Raghunathan, B., Turakhia, Y., Garg, S. & Marculescu, D., 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. Institute of Electrical and Electronics Engineers Inc., p. 39-44 6 p. 6513469. (Proceedings -Design, Automation and Test in Europe, DATE).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Cross-layer reliability modeling and optimization for embedded systems under process variations

    Garg, S., Gupta, P., Patel, H. D. & Shafique, M., 2013, 2013 Proceedings of the International Conference on Embedded Software, EMSOFT 2013. IEEE Computer Society, 6658578. (2013 Proceedings of the International Conference on Embedded Software, EMSOFT 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Cross-layer reliability modeling and optimization for embedded systems under process variations

    Garg, S., Gupta, P., Patel, H. D. & Shafique, M., 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013. IEEE Computer Society, 6658987. (2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Cross-layer reliability modeling and optimization for embedded systems under process variations

    Garg, S., Gupta, P., Patel, H. D. & Shafique, M., 2013, 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013. IEEE Computer Society, 6662504. (2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Custom Feedback Control: Enabling truly scalable on-chip power management for MPSoCs

    Garg, S., Marculescu, D. & Marculescu, R., 2010, ISLPED'10 - Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design. p. 425-430 6 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Dark silicon as a challenge for hardware/software co-design

    Shafique, M., Garg, S., Mitra, T., Parameswaran, S. & Henkel, J., Oct 12 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014. Association for Computing Machinery, Inc, a13. (2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Dark silicon - From computation to communication

    Henkel, J., Bukhari, H., Garg, S., Khan, M. U. K., Khdr, H., Kriebel, F., Ogras, U., Parameswaran, S. & Shafique, M., Sep 28 2015, Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015. Marculescu, D., Ivanov, A., Pande, P. P. & Flich, J. (eds.). Association for Computing Machinery, Inc, 2788707. (Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip

    Ravishankar, C., Ananthanarayan, S., Garg, S. & Kennings, A., 2012, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 41-48 8 p. 6339239. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Energy-efficient computing from systems-on-chip to micro-server and data centers

    Bogdan, P., Garg, S. & Ogras, U. Y., Jan 26 2016, 2015 6th International Green and Sustainable Computing Conference. Institute of Electrical and Electronics Engineers Inc., 7393686. (2015 6th International Green and Sustainable Computing Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Energy efficient scheduling for web search on heterogeneous microservers

    Jain, S., Navale, H., Ogras, U. & Garg, S., Sep 21 2015, Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015. Institute of Electrical and Electronics Engineers Inc., p. 177-182 6 p. 7273510. (Proceedings of the International Symposium on Low Power Electronics and Design; vol. 2015-September).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    FATE: Fast and accurate timing error prediction framework for low power DNN accelerator design

    Zhang, J. J. & Garg, S., Nov 5 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a24. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Fine-pruning: Defending against backdooring attacks on deep neural networks

    Liu, K., Dolan-Gavitt, B. & Garg, S., 2018, Research in Attacks, Intrusions, and Defenses - 21st International Symposium, RAID 2018, Proceedings. Bailey, M., Ioannidis, S., Stamatogiannakis, M. & Holz, T. (eds.). Springer Verlag, p. 273-294 22 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 11050 LNCS).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    HaDeS: Architectural synthesis for heterogeneous dark silicon chip multi-processors

    Turakhia, Y., Raghunathan, B., Garg, S. & Marculescu, D., 2013, Proceedings of the 50th Annual Design Automation Conference, DAC 2013. p. 1-6 6 p. 173. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    IC Decamouaging: Reverse Engineering Camouflaged ICs within Minutes.

    El Massad, M., Garg, S. & Tripunitara, M. V., 2015, Proceedings - Network and Distributed System Security Symposium (NDSS). p. 1-14 14 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Impact of manufacturing process variations on performance and thermal characteristics of 3D ICs: Emerging challenges and new solutions

    Juan, D. C., Garg, S. & Marculescu, D., 2013, 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013. p. 541-544 4 p. 6571900. (Proceedings - IEEE International Symposium on Circuits and Systems).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Inspiring trust in outsourced integrated circuit fabrication

    Garg, S., May 11 2017, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., 1 p. 7927158. (Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    INVITED: Building robust machine learning systems: Current progress, research challenges, and opportunities

    Zhang, J. J., Liu, K., Khalid, F., Hanif, M. A., Rehman, S., Theocharides, T., Artussi, A., Shafique, M. & Garg, S., Jun 2 2019, Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., a175. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    IoT-enabled distributed cyber-attacks on transmission and distribution grids

    Dvorkin, Y. & Garg, S., Nov 13 2017, 2017 North American Power Symposium, NAPS 2017. Institute of Electrical and Electronics Engineers Inc., 8107363. (2017 North American Power Symposium, NAPS 2017).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Is Register Transfer Level Locking Secure?

    Karfa, C., Chouksey, R., Pilato, C., Garg, S. & Karri, R., Mar 2020, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 550-555 6 p. 9116261. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Job arrival rate aware scheduling for asymmetric multi-core servers in the dark silicon era

    Raghunathan, B. & Garg, S., Oct 12 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014. Association for Computing Machinery, Inc, p. 1-6 6 p. a14. (2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Lack of robustness of Lidar-based deep learning systems to small adversarial perturbations

    Patel, N., Liu, K., Krishnamurthy, P., Garg, S. & Khorrami, F., 2018, 50th International Symposium on Robotics, ISR 2018. VDE Verlag GmbH, p. 359-365 7 p. (50th International Symposium on Robotics, ISR 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Learning the optimal operating point for many-core systems with extended range voltage/frequency scaling

    Juan, D. C., Garg, S., Park, J. & Marculescu, D., 2013, 2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013. IEEE Computer Society, p. 1-10 10 p. 6658995. (2013 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Low cost permanent fault detection using ultra-reduced instruction set co-processors

    Ananthanarayan, S., Garg, S. & Patel, H. D., 2013, Proceedings - Design, Automation and Test in Europe, DATE 2013. Institute of Electrical and Electronics Engineers Inc., p. 933-938 6 p. 6513642. (Proceedings -Design, Automation and Test in Europe, DATE).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Matching Graphs with Community Structure: A Concentration of Measure Approach

    Shirani, F., Garg, S. & Erkip, E., Feb 5 2019, 2018 56th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2018. Institute of Electrical and Electronics Engineers Inc., p. 1028-1035 8 p. 8636015. (2018 56th Annual Allerton Conference on Communication, Control, and Computing, Allerton 2018).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    On the impact of manufacturing process variations on the lifetime of sensor networks

    Garg, S. & Marculescu, D., 2007, CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. p. 203-208 6 p. (CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Optimal Active social Network De-anonymization Using Information Thresholds

    Shirani, F., Garg, S. & Erkip, E., Aug 15 2018, 2018 IEEE International Symposium on Information Theory, ISIT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1445-1449 5 p. 8437739. (IEEE International Symposium on Information Theory - Proceedings; vol. 2018-June).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Optimal checkpointing for secure intermittently-powered IoT devices

    Ghodsi, Z., Garg, S. & Karri, R., Dec 13 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., p. 376-383 8 p. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2017-November).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Optimal de-anonymization in random graphs with community structure

    Onaran, E., Garg, S. & Erkip, E., Mar 1 2017, Conference Record of the 50th Asilomar Conference on Signals, Systems and Computers, ACSSC 2016. Matthews, M. B. (ed.). IEEE Computer Society, p. 709-713 5 p. 7869137. (Conference Record - Asilomar Conference on Signals, Systems and Computers).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Optimal de-anonymization in random graphs with community structure

    Onaran, E., Garg, S. & Erkip, E., Feb 7 2017, 37th IEEE Sarnoff Symposium, Sarnoff 2016. Institute of Electrical and Electronics Engineers Inc., 7846734. (37th IEEE Sarnoff Symposium, Sarnoff 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic Hotspots

    Liu, K., Tan, B., Karri, R. & Garg, S., Mar 2020, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Di Natale, G., Bolchini, C. & Vatajelu, E-I. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 306-309 4 p. 9116489. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Power-aware virtual machine mapping in the data-center-on-a-chip paradigm

    Lin, X., Xue, Y., Bogdan, P., Wang, Y., Garg, S. & Pedram, M., Nov 22 2016, Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016. Institute of Electrical and Electronics Engineers Inc., p. 241-248 8 p. 7753286. (Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Process variation aware performance modeling and dynamic power management for multi-core systems

    Garg, S., Marculescu, D. & Herbert, S. X., 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2010. p. 89-92 4 p. 5654293. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Reliable computing with ultra-reduced instruction set co-processors

    Rajendiran, A., Ananthanarayanan, S., Patel, H. D., Tripunitara, M. V. & Garg, S., 2012, Proceedings of the 49th Annual Design Automation Conference, DAC '12. p. 697-702 6 p. (Proceedings - Design Automation Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Resource sharing games with failures and heterogeneous risk attitudes

    Hota, A. R., Garg, S. & Sundaram, S., 2013, 2013 51st Annual Allerton Conference on Communication, Control, and Computing, Allerton 2013. IEEE Computer Society, p. 535-542 8 p. 6736571. (2013 51st Annual Allerton Conference on Communication, Control, and Computing, Allerton 2013).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Rethinking split manufacturing: An information-theoretic approach with secure layout techniques

    Sengupta, A., Patnaik, S., Knechtel, J., Ashraf, M., Garg, S. & Sinanoglu, O., Dec 13 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., p. 329-336 8 p. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2017-November).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Reverse engineering camouflaged sequential circuits without scan access

    Massad, M. E., Garg, S. & Tripunitara, M., Dec 13 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017. Institute of Electrical and Electronics Engineers Inc., p. 33-40 8 p. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; vol. 2017-November).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

    Mera Collantes, M. I., Ghodsi, Z. & Garg, S., Apr 2020, Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 9107564. (Proceedings of the IEEE VLSI Test Symposium; vol. 2020-April).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation

    Imeson, F., Emtenan, A., Garg, S. & Tripunitara, M. V., Jan 1 2013, Proceedings of the 22nd USENIX Security Symposium. USENIX Association, p. 495-510 16 p. (Proceedings of the 22nd USENIX Security Symposium).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Seeded graph matching: Efficient algorithms and theoretical guarantees

    Shirani, F., Garg, S. & Erkip, E., Apr 10 2018, Conference Record of 51st Asilomar Conference on Signals, Systems and Computers, ACSSC 2017. Matthews, M. B. (ed.). Institute of Electrical and Electronics Engineers Inc., p. 253-257 5 p. 8335178. (Conference Record of 51st Asilomar Conference on Signals, Systems and Computers, ACSSC 2017; vol. 2017-October).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shielding and securing integrated circuits using sensors

    Shahrjerdi, D., Rajendran, J., Garg, S., Koushanfar, F. & Karri, R., Nov 2014, Proceedings of the IEEE International Conference on CAD. p. 170-174

    Research output: Chapter in Book/Report/Conference proceedingConference contribution