����ℰℱect ����olerant layout synthesis

A mismatch between the decrease in feet-densities and the increase in senstivity to defects of integrated circuits (lCs) is contributing towards deteriorating chip yields, in even the most advanced of IC fabrication lines. This unprofitable trend in IC yields can be arrested and even reversed by using two main techniques. The defect densities of an IC fabrication line can be minimized by tuning the process parameters. However, a zero-defect manufacturing line is a myth. Along an orthogonal dimension, the sensitivity of circuit structures to defects can be minimized by making them defect-tolerant. In this paper we present ����ℰℱ����, a system for synthesizing such defect-tolerant layouts. ����ℰℱ���� ingrains tolerance to fabrication induced defects by reducing the defect-sensitive areas in a layout and this is accomplished by dispersing nets with large overlaps into non-adjacent tracks. Furthermore, ����ℰℱ���� affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by ����ℰℱ���� have been consistently superior to those generated by other layout synthesis systems.