3D Integrated Circuits (ICs) have been re- cently proposed as a solution to the increasing wire delay concerns in scaled technologies. At the same time, technol- ogy scaling leads to increasing variability in manufacturing process parameters, making it imperative to quantify the impact of these variations on performance. In this work, we take, to the best of our knowledge, the first step towards formally modeling the impact of process variations on the clock frequency of fully-synchronous (FS) 3D ICs. The proposed analytical models demonstrate theoretically and experimentally that 3D designs behave very di erently under the impact of process variations as compared to equivalent 2D designs. In particular, for the same number of critical paths, we show that a 3D design is always less likely to meet a pre-de ned frequency target compared to its 2D counterpart. Further more, as opposed to models for 2D ICs, the 3D models need to accurately account for not only within-die (WID) critical paths, i.e., paths that lie entirely within one of the die layers, but also D2D critical paths that use through- silicon vias (TSVs) to span across multiple dies in the 3D stack. Finally, we show, theoretically and experimentally, that the mapping of critical paths to the die layers of a 3D IC can also a ect the timing yield of a design, while the mapping issue does not arise in the 2D case since there is only a single die layer in a 2D IC. The accuracy of the proposed models is experimentally veri ed and found to be in excellent agreement with detailed SPICE and gate-level Monte Carlo (MC) simulations.