TY - GEN
T1 - A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch
AU - Choi, Edward
AU - Lukito, Vincent
AU - Choi, Injun
AU - Lee, Seoyoung
AU - Chang, Ik Joon
AU - Ha, Sohmyung
AU - Je, Minkyu
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The proposed Δ -based spike sorting (SS) SoC is the first on-chip implementation of an analog computing-in-memory (CIM) binary autoencoder neural network (B-AENN) feature extraction with enhanced spike detection adopting Δ -spikes, resulting in the highest on-chip SS classification accuracy of 94.54%. It also allows to reduce the digital data transmission rate by 48.8× compared to prior SS systems.
AB - The proposed Δ -based spike sorting (SS) SoC is the first on-chip implementation of an analog computing-in-memory (CIM) binary autoencoder neural network (B-AENN) feature extraction with enhanced spike detection adopting Δ -spikes, resulting in the highest on-chip SS classification accuracy of 94.54%. It also allows to reduce the digital data transmission rate by 48.8× compared to prior SS systems.
UR - http://www.scopus.com/inward/record.url?scp=85203585636&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85203585636&partnerID=8YFLogxK
U2 - 10.1109/VLSITechnologyandCir46783.2024.10631554
DO - 10.1109/VLSITechnologyandCir46783.2024.10631554
M3 - Conference contribution
AN - SCOPUS:85203585636
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Y2 - 16 June 2024 through 20 June 2024
ER -