TY - GEN
T1 - A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero
AU - Shin, Hongseok
AU - Kim, Jinuk
AU - Jang, Doojin
AU - Cho, Donghee
AU - Jung, Yoontae
AU - Cho, Hyungjoo
AU - Lee, Unbong
AU - Kim, Chul
AU - Ha, Sohmyung
AU - Je, Minkyu
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/6
Y1 - 2020/6
N2 - This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOML by 1.36 times, LC-FOMS by 1.26 times, and LC-FOML by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.
AB - This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOML by 1.36 times, LC-FOMS by 1.26 times, and LC-FOML by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.
UR - http://www.scopus.com/inward/record.url?scp=85090238458&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85090238458&partnerID=8YFLogxK
U2 - 10.1109/VLSICircuits18222.2020.9162960
DO - 10.1109/VLSICircuits18222.2020.9162960
M3 - Conference contribution
AN - SCOPUS:85090238458
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
BT - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Y2 - 16 June 2020 through 19 June 2020
ER -