A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

Hongseok Shin; Jinuk Kim; Doojin Jang; Donghee Cho; Yoontae Jung; Hyungjoo Cho; Unbong Lee; Chul Kim; Sohmyung Ha; Minkyu Je

doi:10.1109/VLSICircuits18222.2020.9162960

A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

Hongseok Shin, Jinuk Kim, Doojin Jang, Donghee Cho, Yoontae Jung, Hyungjoo Cho, Unbong Lee, Chul Kim, Sohmyung Ha, Minkyu Je

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOM_L by 1.36 times, LC-FOM_S by 1.26 times, and LC-FOM_L by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.

Original language	English (US)
Title of host publication	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728199429
DOIs	https://doi.org/10.1109/VLSICircuits18222.2020.9162960
State	Published - Jun 2020
Event	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Honolulu, United States Duration: Jun 16 2020 → Jun 19 2020

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2020-June

Conference

Conference	2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020
Country/Territory	United States
City	Honolulu
Period	6/16/20 → 6/19/20

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/VLSICircuits18222.2020.9162960

Cite this

Shin, H., Kim, J., Jang, D., Cho, D., Jung, Y., Cho, H., Lee, U., Kim, C., Ha, S., & Je, M. (2020). A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings Article 9162960 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSICircuits18222.2020.9162960

A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. / Shin, Hongseok; Kim, Jinuk; Jang, Doojin et al.
2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9162960 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2020-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shin, H, Kim, J, Jang, D, Cho, D, Jung, Y, Cho, H, Lee, U, Kim, C, Ha, S & Je, M 2020, A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. in 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings., 9162960, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2020-June, Institute of Electrical and Electronics Engineers Inc., 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, United States, 6/16/20. https://doi.org/10.1109/VLSICircuits18222.2020.9162960

Shin H, Kim J, Jang D, Cho D, Jung Y, Cho H et al. A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. In 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9162960. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSICircuits18222.2020.9162960

Shin, Hongseok ; Kim, Jinuk ; Jang, Doojin et al. / A 0.0046mm² 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero. 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOML by 1.36 times, LC-FOMS by 1.26 times, and LC-FOML by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.",

author = "Hongseok Shin and Jinuk Kim and Doojin Jang and Donghee Cho and Yoontae Jung and Hyungjoo Cho and Unbong Lee and Chul Kim and Sohmyung Ha and Minkyu Je",

note = "Funding Information: in Fig. 5, the proposed design achieves improved FOML (1.36), LC-FOMS (1.26), and LC-FOML (3.18). The design has been fabricated in a 0.18μm CMOS process, occupying 0.0046mm2 (Fig. 6). The amplifier consumes 6.7μW at a 1V supply, while the additional consumption for the buffer and AUX path is only 0.91μW (Fig. 3). Acknowledgements: This work was supported by National Research Foundation of Korea (NRF-2017M3C1B2085296) and Samsung Electronics (Future Interconnect Technology Cluster Program). Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 ; Conference date: 16-06-2020 Through 19-06-2020",

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