TY - GEN
T1 - A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation
AU - Ha, S.
AU - Akinin, A.
AU - Park, J.
AU - Kim, C.
AU - Wang, H.
AU - Maier, C.
AU - Cauwenberghs, G.
AU - Mercier, P. P.
N1 - Publisher Copyright:
© 2015 JSAP.
PY - 2015/8/31
Y1 - 2015/8/31
N2 - This paper presents a fully-integrated 16-channel wireless neural interfacing SoC that employs an adiabatic stimulator powered directly from a 190-MHz on-chip antenna to eliminate bulky external components while simultaneously avoiding rectifier and regulator losses. Using a charge replenishing architecture, the stimulator outputs up to 145-μA, while achieving a 63.1% charge replenishing ratio and a stimulation efficiency factor of 6.0. Analog front-ends (AFEs) and telemetry circuitry are also included.
AB - This paper presents a fully-integrated 16-channel wireless neural interfacing SoC that employs an adiabatic stimulator powered directly from a 190-MHz on-chip antenna to eliminate bulky external components while simultaneously avoiding rectifier and regulator losses. Using a charge replenishing architecture, the stimulator outputs up to 145-μA, while achieving a 63.1% charge replenishing ratio and a stimulation efficiency factor of 6.0. Analog front-ends (AFEs) and telemetry circuitry are also included.
UR - http://www.scopus.com/inward/record.url?scp=84957883493&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84957883493&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2015.7231341
DO - 10.1109/VLSIC.2015.7231341
M3 - Conference contribution
AN - SCOPUS:84957883493
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C106-C107
BT - 2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Y2 - 17 June 2015 through 19 June 2015
ER -