A 187-dB FoM_S Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter

The escalating demand for high-resolution sensor interface systems, driven by the proliferation of the Internet of Things (IoT) and wearable smart devices, has led to the widespread use of capacitive sensing transducers. These transducers are valued for their low-noise and low-power characteristics, making them suitable for various applications, including environmental and biomedical sensing. However, designing a high-resolution capacitive sensor interface system while maintaining power efficiency remains challenging. This article proposes a high-resolution energy-efficient highpass (HP) Δ Σ capacitance-to-digital converter (CDC) architecture. The architecture incorporates a 2nd-order HP Δ Σ modulator (Δ Σ M ) and a continuous-time capacitance-to-voltage converter (CT CVC). The proposed CDC achieves an excellent capacitance resolution of 5.85 aFrms, with a power efficiency of 46 fJ/conversion-step and an FoMS of 187.4 dB. The HP Δ Σ M , designed with superior power efficiency, offers a promising solution for high-resolution capacitive sensor applications. Compared to state-of-the-art, the proposed CDC achieves more than 2× FoMS improvement while maintaining competitive FoMW.