A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers

Sein Oh, Seunga Park, Yoontae Jung, Jimin Koo, Donghee Cho, Sohmyung Ha, Minkyu Je

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 4th-order passive bandpass Δ Σ modulator (BPDSM) using a 2- path transformation structure is presented. The proposed BPDSM replaces a power-hungry resonator with a z-to-z2-transformed passive loop filter. The prototype bandpass Δ Σ ADC provides a wide intermediate frequency (IF) range of 1.25MHz to 60MHz. The measured SNDR is 69dB with a power consumption of 2.5mW at 12MHz bandwidth when its highest sampling rate is 240MS/s.

Original languageEnglish (US)
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
StatePublished - 2023
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: Jun 11 2023Jun 16 2023

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period6/11/236/16/23

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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