A 333TOPS/W Logic-Compatible Multi-Level Embedded Flash Compute-In-Memory Macro with Dual-Slope Computation

Edward Choi, Injun Choi, Vincent Lukito, Dong Hwi Choi, Donghyeon Yi, Ik Joon Chang, Sohmyung Ha, Minkyu Je

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Computing-in-memory (CIM) has been an ongoing prominent research area for easing the energy efficiency of machine learning tasks in edge devices. Recently, embedded non-volatile memory (eNVM) CIM architectures have been popular as an edge device, where it can turn off their supply during standby for low power consumption. However, most eNVMs (e.g., MRAMs and RRAMs) require the use of specialized technologies and are mostly used as single-level cell (SLC) data storage [2], [3]. In the technologies that do not provide eNVMs, logic-compatible single-poly non-volatile embedded flash (eflash) memory [1] can be considered an alternative. Although the cell area of the single-poly non-volatile eflash is significant, we can considerably compensate for the cell area penalty by using multi-level cells (MLCS). Further, in eNVM CIMs, the analog computations must be quantized with an ADC, where the SAR ADCs are a popular conversion topology. However, SAR ADC designs result in significant power consumption and area overhead due to its capacitor DAC driving and high accuracy comparators [5]. In this work, we propose to overcome such challenges by proposing 1) a logic-compatible single-poly nonvolatile eflash memory macro using MLC and an SLC at the same time to increase computation density while maintaining a reasonable signal margin, 2) a resolution configurable differential SAR TDC used for both memory programming and computing with replacing analog voltage comparators to inverters in order to reduce power consumption and area, and 3) an energy-efficient 2's complement dual-slope computation with MLC and SLC sharing a single differential TDC for multi-bit weight computation. We fabricated the proposed eFlash CIM macro in a 65 ~nm CMOS process. Our measurements show that the proposed CIM macro achieves up to 333 TOPSM energy efficiency and 186.2 GOPS throughput.

Original languageEnglish (US)
Title of host publication2023 IEEE Custom Integrated Circuits Conference, CICC 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350399486
StatePublished - 2023
Event44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023 - San Antonio, United States
Duration: Apr 23 2023Apr 26 2023

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930


Conference44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023
Country/TerritoryUnited States
CitySan Antonio

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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