TY - JOUR
T1 - A 500-MHz Bandwidth 7.5-mVpp Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters
AU - Kim, Chul
AU - Chae, Chang Seok
AU - Yuk, Young Sub
AU - Thomas, Chris M.
AU - Kim, Yi Gyeong
AU - Kwon, Jong Kee
AU - Ha, Sohmyung
AU - Cauwenberghs, Gert
AU - Cho, Gyu Hyeong
N1 - Funding Information:
Manuscript received May 29, 2017; revised September 23, 2017 and January 1, 2018; accepted January 25, 2018. Date of publication February 28, 2018; date of current version May 24, 2018. This work was supported by IT R&D program of MKE/IITA, South Korea. This paper was approved by Associate Editor Yogesh Ramadass. (Corresponding author: Chul Kim.) C. Kim and G. Cauwenberghs are with the Department of Bioengineering, UC San Diego, La Jolla, CA 92093 USA (e-mail: [email protected]). C.-S. Chae is with Samsung Electronics, Hwaseong 18448, South Korea. Y.-S. Yuk is with SK Hynix, Icheon 17336, South Korea. C. M. Thomas is with MaXentric, La Jolla, CA 92037 USA. Y.-G. Kim and J.-K. Kwon are with the Mixed-Signal Product Engineering Department, Electronics and Telecommunications Research Institute, Daejeon 34129, South Korea. S. Ha is with the Department of Electrical and Computer Engineering, New York University Abu Dhabi, Abu Dhabi 129188, UAE. G.-H. Cho is with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 34141, South Korea. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2018.2804043 Fig. 1. (a) Architecture of a polar modulated transmitter. (b) Power spectral density of polar modulated signals.
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - The parallel combination of a switching and a linear amplifier in the supply modulator for RF power amplifiers (PAs) has the potential to enhance energy efficiency while achieving wider bandwidth and lower ripple output voltage. In this paper, a linear amplifier that features a buffered-switching Class-AB bias scheme is presented for the supply modulator in polar-transmitter structures achieving 500 MHz of small-signal 3-dB bandwidth at a 1.2-V supply. The linear amplifier absorbs and cancels up to 60 mA of ripple current from the switching amplifier. As such, the ripple in the output voltage of the hybrid linear-switching supply modulator is less than 7.5 mVpp. The switching amplifier provides most of the signal current for greatest efficiency owing to a proposed rail-to-rail current-sensing circuit. Current feedback in the switching amplifier achieves 1.68-MHz unity-gain bandwidth at 6-MHz switching frequency. Harmonic distortion in the output voltage of the supply modulator is below 40 dBc at 0.8 Vpp sinusoidal input up to 9 MHz. The peak efficiency is 87.7% for a 8.25- Ω load, while the maximum output power is 23.6 dBm for a 4.99- Ω load. The chip measures 1.35 mm2 in a 65-nm standard bulk CMOS process.
AB - The parallel combination of a switching and a linear amplifier in the supply modulator for RF power amplifiers (PAs) has the potential to enhance energy efficiency while achieving wider bandwidth and lower ripple output voltage. In this paper, a linear amplifier that features a buffered-switching Class-AB bias scheme is presented for the supply modulator in polar-transmitter structures achieving 500 MHz of small-signal 3-dB bandwidth at a 1.2-V supply. The linear amplifier absorbs and cancels up to 60 mA of ripple current from the switching amplifier. As such, the ripple in the output voltage of the hybrid linear-switching supply modulator is less than 7.5 mVpp. The switching amplifier provides most of the signal current for greatest efficiency owing to a proposed rail-to-rail current-sensing circuit. Current feedback in the switching amplifier achieves 1.68-MHz unity-gain bandwidth at 6-MHz switching frequency. Harmonic distortion in the output voltage of the supply modulator is below 40 dBc at 0.8 Vpp sinusoidal input up to 9 MHz. The peak efficiency is 87.7% for a 8.25- Ω load, while the maximum output power is 23.6 dBm for a 4.99- Ω load. The chip measures 1.35 mm2 in a 65-nm standard bulk CMOS process.
KW - Class-AB bias
KW - current feedback
KW - current sensing
KW - envelope elimination and restoration
KW - hybrid supply modulator (HSM)
KW - open-loop gate driver polar transmitter
KW - three-stage amplifier
KW - wide bandwidth
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U2 - 10.1109/JSSC.2018.2804043
DO - 10.1109/JSSC.2018.2804043
M3 - Article
AN - SCOPUS:85042865724
SN - 0018-9200
VL - 53
SP - 1653
EP - 1665
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -