A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording

Yegeun Kim; Changhun Seok; Kyeongwon Jeong; Haidam Choi; Heewon Choee; Sohmyung Ha; Minkyu Je

doi:10.1109/ESSERC62670.2024.10719405

A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording

Yegeun Kim, Changhun Seok, Kyeongwon Jeong, Haidam Choi, Heewon Choee, Sohmyung Ha, Minkyu Je

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work presents a 3rd-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing an error feedback-cascaded integrator feedforward (EF-CIFF) structure where a low-noise amplifier (LNA) is embedded, which operates for neural recording at a low oversampling ratio (OSR). By employing the 3rd-order EFCIFF NS-SAR ADC and embedded low-gain LNA, it achieves low input-referred noise (IRN) while offering a sufficiently wide input range so that stimulation artifacts can be accommodated when applied to closed-loop neural interface systems. By reusing the LNA, it can implement PVT-robust charge summation with good driving ability in the error feedback (EF) path without consuming additional power. Fabricated in a 180-nm CMOS process, the proposed IC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 80.8 dB with an OSR of 16 and a 2.5 kHz signal bandwidth (BW), while consuming 5.3 μW from a 1.2V supply. This results in a Schreier's figure of merit (FOM) of 167.5 dB.

Original language	English (US)
Title of host publication	ESSERC 2024 - Proceedings
Subtitle of host publication	50th IEEE European Solid-State Electronics Research Conference
Publisher	IEEE Computer Society
Pages	645-648
Number of pages	4
ISBN (Electronic)	9798350388138
DOIs	https://doi.org/10.1109/ESSERC62670.2024.10719405
State	Published - 2024
Event	50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024 - Bruges, Belgium Duration: Sep 9 2024 → Sep 12 2024

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024
Country/Territory	Belgium
City	Bruges
Period	9/9/24 → 9/12/24

Keywords

amplifier-embedded
closed-loop neural recording
noise-shaping
successive approximation register (SAR)

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSERC62670.2024.10719405

Cite this

Kim, Y., Seok, C., Jeong, K., Choi, H., Choee, H., Ha, S., & Je, M. (2024). A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording. In ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference (pp. 645-648). (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSERC62670.2024.10719405

A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording. / Kim, Yegeun; Seok, Changhun; Jeong, Kyeongwon et al.
ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. IEEE Computer Society, 2024. p. 645-648 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, Y, Seok, C, Jeong, K, Choi, H, Choee, H, Ha, S & Je, M 2024, A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording. in ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. European Solid-State Circuits Conference, IEEE Computer Society, pp. 645-648, 50th IEEE European Solid-State Electronics Research Conference, ESSERC 2024, Bruges, Belgium, 9/9/24. https://doi.org/10.1109/ESSERC62670.2024.10719405

Kim Y, Seok C, Jeong K, Choi H, Choee H, Ha S et al. A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording. In ESSERC 2024 - Proceedings: 50th IEEE European Solid-State Electronics Research Conference. IEEE Computer Society. 2024. p. 645-648. (European Solid-State Circuits Conference). doi: 10.1109/ESSERC62670.2024.10719405

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abstract = "This work presents a 3rd-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing an error feedback-cascaded integrator feedforward (EF-CIFF) structure where a low-noise amplifier (LNA) is embedded, which operates for neural recording at a low oversampling ratio (OSR). By employing the 3rd-order EFCIFF NS-SAR ADC and embedded low-gain LNA, it achieves low input-referred noise (IRN) while offering a sufficiently wide input range so that stimulation artifacts can be accommodated when applied to closed-loop neural interface systems. By reusing the LNA, it can implement PVT-robust charge summation with good driving ability in the error feedback (EF) path without consuming additional power. Fabricated in a 180-nm CMOS process, the proposed IC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 80.8 dB with an OSR of 16 and a 2.5 kHz signal bandwidth (BW), while consuming 5.3 μW from a 1.2V supply. This results in a Schreier's figure of merit (FOM) of 167.5 dB.",

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AB - This work presents a 3rd-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing an error feedback-cascaded integrator feedforward (EF-CIFF) structure where a low-noise amplifier (LNA) is embedded, which operates for neural recording at a low oversampling ratio (OSR). By employing the 3rd-order EFCIFF NS-SAR ADC and embedded low-gain LNA, it achieves low input-referred noise (IRN) while offering a sufficiently wide input range so that stimulation artifacts can be accommodated when applied to closed-loop neural interface systems. By reusing the LNA, it can implement PVT-robust charge summation with good driving ability in the error feedback (EF) path without consuming additional power. Fabricated in a 180-nm CMOS process, the proposed IC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 80.8 dB with an OSR of 16 and a 2.5 kHz signal bandwidth (BW), while consuming 5.3 μW from a 1.2V supply. This results in a Schreier's figure of merit (FOM) of 167.5 dB.

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A 5.3-μW 80.8-dB SNDR LNA-Embedded EF-CIFF Third-Order Noise-Shaping SAR ADC for Closed-Loop Neural Recording

Abstract

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Keywords

ASJC Scopus subject areas

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