We present a 65k-neuron integrate-and-fire array transceiver (IFAT) for spike-based neural computation with low-power, high-throughput connectivity. The internally analog, externally digital chip is fabricated on a 4×4 mm2 die in 90nm CMOS and arranged in 4 quadrants of 16k parallel addressable neurons. Each neuron circuit serves input spike events by dynamically instantiating conductance-based synapses onto four local synapse circuits over two membrane compartments, and produces output spike events upon reaching a threshold in integration over one of the membrane compartments. Fully asynchronous input and output spike event data streams are mediated over the standard address event representation (AER) protocol. To support full event throughput at large synaptic fan-in, a two-tier micro-pipelining scheme parallelizes input events along neural array cores, and along rows of each core. Measured results show sustained peak synaptic event throughput of 18.2 Mevents/s per quadrant, at 22 pJ average energy per synaptic input event and 25 μW standby power.