TY - GEN
T1 - A 65k-neuron 73-Mevents/s 22-pJ/event asynchronous micro-pipelined integrate-and-fire array transceiver
AU - Park, Jongkil
AU - Ha, Sohmyung
AU - Yu, Theodore
AU - Neftci, Emre
AU - Cauwenberghs, Gert
PY - 2014/12/9
Y1 - 2014/12/9
N2 - We present a 65k-neuron integrate-and-fire array transceiver (IFAT) for spike-based neural computation with low-power, high-throughput connectivity. The internally analog, externally digital chip is fabricated on a 4×4 mm2 die in 90nm CMOS and arranged in 4 quadrants of 16k parallel addressable neurons. Each neuron circuit serves input spike events by dynamically instantiating conductance-based synapses onto four local synapse circuits over two membrane compartments, and produces output spike events upon reaching a threshold in integration over one of the membrane compartments. Fully asynchronous input and output spike event data streams are mediated over the standard address event representation (AER) protocol. To support full event throughput at large synaptic fan-in, a two-tier micro-pipelining scheme parallelizes input events along neural array cores, and along rows of each core. Measured results show sustained peak synaptic event throughput of 18.2 Mevents/s per quadrant, at 22 pJ average energy per synaptic input event and 25 μW standby power.
AB - We present a 65k-neuron integrate-and-fire array transceiver (IFAT) for spike-based neural computation with low-power, high-throughput connectivity. The internally analog, externally digital chip is fabricated on a 4×4 mm2 die in 90nm CMOS and arranged in 4 quadrants of 16k parallel addressable neurons. Each neuron circuit serves input spike events by dynamically instantiating conductance-based synapses onto four local synapse circuits over two membrane compartments, and produces output spike events upon reaching a threshold in integration over one of the membrane compartments. Fully asynchronous input and output spike event data streams are mediated over the standard address event representation (AER) protocol. To support full event throughput at large synaptic fan-in, a two-tier micro-pipelining scheme parallelizes input events along neural array cores, and along rows of each core. Measured results show sustained peak synaptic event throughput of 18.2 Mevents/s per quadrant, at 22 pJ average energy per synaptic input event and 25 μW standby power.
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U2 - 10.1109/BioCAS.2014.6981816
DO - 10.1109/BioCAS.2014.6981816
M3 - Conference contribution
AN - SCOPUS:84920548116
T3 - IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings
SP - 675
EP - 678
BT - IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Biomedical Circuits and Systems Conference, BioCAS 2014
Y2 - 22 October 2014 through 24 October 2014
ER -