TY - GEN
T1 - A 700 μw 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications
AU - Nasri, Bayan
AU - Sebastian, Sunit P.
AU - You, Kae Dyi
AU - Ranjithkumar, Ramkumar
AU - Shahrjerdi, Davood
N1 - Funding Information:
V. ACKNOWLEDGMENTS The authors acknowledge Prof. Sundeep Rangan for helpful discussions. This work is supported in part by NYU WIRELESS and United Microelectronics Corporation (UMC).
Publisher Copyright:
© 2017 IEEE.
PY - 2017/9/25
Y1 - 2017/9/25
N2 - We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two in standard 65nm CMOS technology. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the conventional approaches, this design uses a fully matched input stage, an unbalanced latch stage, and a two-clock operation scheme. A combination of these features yields significant reduction of the kick-back noise, while allowing the design flexibility for adjusting the trip points of the comparators. As a result, the ADC achieves SNDR of 22.3 dB at 100MHz and 21.8 dB at 500MHz (i.e. the Nyquist frequency). The maximum INL and DNL are about 0.2 LSB. The converter consumes about 700μW from a 1-V supply yielding a figure of merit of 65fJ/conversion step. These attributes make the proposed folding-flash ADC attractive for the next-generation wireless applications.
AB - We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two in standard 65nm CMOS technology. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the conventional approaches, this design uses a fully matched input stage, an unbalanced latch stage, and a two-clock operation scheme. A combination of these features yields significant reduction of the kick-back noise, while allowing the design flexibility for adjusting the trip points of the comparators. As a result, the ADC achieves SNDR of 22.3 dB at 100MHz and 21.8 dB at 500MHz (i.e. the Nyquist frequency). The maximum INL and DNL are about 0.2 LSB. The converter consumes about 700μW from a 1-V supply yielding a figure of merit of 65fJ/conversion step. These attributes make the proposed folding-flash ADC attractive for the next-generation wireless applications.
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U2 - 10.1109/ISCAS.2017.8050624
DO - 10.1109/ISCAS.2017.8050624
M3 - Conference contribution
AN - SCOPUS:85032662538
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Y2 - 28 May 2017 through 31 May 2017
ER -