A 700 μw 1GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications

Bayan Nasri, Sunit P. Sebastian, Kae Dyi You, Ramkumar Ranjithkumar, Davood Shahrjerdi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present the design of a low-power 4-bit 1GS/s folding-flash ADC with a folding factor of two in standard 65nm CMOS technology. The design of a new unbalanced double-tail dynamic comparator affords an ultra-low power operation and a high dynamic range. Unlike the conventional approaches, this design uses a fully matched input stage, an unbalanced latch stage, and a two-clock operation scheme. A combination of these features yields significant reduction of the kick-back noise, while allowing the design flexibility for adjusting the trip points of the comparators. As a result, the ADC achieves SNDR of 22.3 dB at 100MHz and 21.8 dB at 500MHz (i.e. the Nyquist frequency). The maximum INL and DNL are about 0.2 LSB. The converter consumes about 700μW from a 1-V supply yielding a figure of merit of 65fJ/conversion step. These attributes make the proposed folding-flash ADC attractive for the next-generation wireless applications.

Original languageEnglish (US)
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
StatePublished - Sep 25 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: May 28 2017May 31 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period5/28/175/31/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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