A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator

Dong Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan Yu Chen; Chaitali Chakrabarti; Michael Bedford Taylor; Trevor Mudge; David Blaauw; Hun Seok Kim; Ronald G. Dreslinski

doi:10.1109/JSSC.2019.2960480

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator

Dong Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor Mudge, David Blaauw, Hun Seok Kim, Ronald G. Dreslinski

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A sparse matrix-matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and compute units are interconnected with synthesizable coalescing crossbars for efficient memory access. The 2.0-mm \times 2.6-mm chip exhibits 12.6 \times (8.4 \times ) energy efficiency gain, 11.7 \times (77.6 \times ) off-chip bandwidth efficiency gain, and 17.1 \times (36.9 \times ) compute density gain s against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph-based sparse matrices.

Original language	English (US)
Article number	8947989
Pages (from-to)	933-944
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	55
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2019.2960480
State	Published - Apr 2020

Keywords

Decoupled access execution
reconfigurablility and accelerator
sparse matrix multiplier
synthesizable crossbar

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2019.2960480

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Park, D. H., Pal, S., Feng, S., Gao, P., Tan, J., Rovinski, A., Xie, S., Zhao, C., Amarnath, A., Wesley, T., Beaumont, J., Chen, K. Y., Chakrabarti, C., Taylor, M. B., Mudge, T., Blaauw, D., Kim, H. S., & Dreslinski, R. G. (2020). A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE Journal of Solid-State Circuits, 55(4), 933-944. Article 8947989. https://doi.org/10.1109/JSSC.2019.2960480

Park, DH, Pal, S, Feng, S, Gao, P, Tan, J, Rovinski, A, Xie, S, Zhao, C, Amarnath, A, Wesley, T, Beaumont, J, Chen, KY, Chakrabarti, C, Taylor, MB, Mudge, T, Blaauw, D, Kim, HS & Dreslinski, RG 2020, 'A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator', IEEE Journal of Solid-State Circuits, vol. 55, no. 4, 8947989, pp. 933-944. https://doi.org/10.1109/JSSC.2019.2960480

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abstract = "A sparse matrix-matrix multiplication (SpMM) accelerator with 48 heterogeneous cores and a reconfigurable memory hierarchy is fabricated in 40-nm CMOS. The compute fabric consists of dedicated floating-point multiplication units, and general-purpose Arm Cortex-M0 and Cortex-M4 cores. The on-chip memory reconfigures scratchpad or cache, depending on the phase of the algorithm. The memory and compute units are interconnected with synthesizable coalescing crossbars for efficient memory access. The 2.0-mm \times 2.6-mm chip exhibits 12.6 \times (8.4 \times ) energy efficiency gain, 11.7 \times (77.6 \times ) off-chip bandwidth efficiency gain, and 17.1 \times (36.9 \times ) compute density gain s against a high-end CPU (GPU) across a diverse set of synthetic and real-world power-law graph-based sparse matrices.",

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AU - Wesley, Timothy

AU - Beaumont, Jonathan

AU - Chen, Kuan Yu

AU - Chakrabarti, Chaitali

AU - Taylor, Michael Bedford

AU - Mudge, Trevor

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A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator

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Keywords

ASJC Scopus subject areas

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