A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS

Chul Kim; Sohmyung Ha; Chris Thomas; Siddharth Joshi; Jongkil Park; Lawrence Larson; Gert Cauwenberghs

doi:10.1109/ESSCIRC.2014.6942063

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS

Chul Kim, Sohmyung Ha, Chris Thomas, Siddharth Joshi, Jongkil Park, Lawrence Larson, Gert Cauwenberghs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3 of +12.5 dBm at 320 MHz LO over 3 MHz baseband. The 1.62mm² mixer in 65nm CMOS consumes 40 μW per I/Q complex output channel, and 7.82 mW for 16-phase PLL clock generation and distribution.

Original language	English (US)
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Editors	Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
Publisher	IEEE Computer Society
Pages	227-230
Number of pages	4
ISBN (Electronic)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942063
State	Published - Oct 31 2014
Event	40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: Sep 22 2014 → Sep 26 2014

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Other

Other	40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/Territory	Italy
City	Venezia Lido
Period	9/22/14 → 9/26/14

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ESSCIRC.2014.6942063

Cite this

Kim, C., Ha, S., Thomas, C., Joshi, S., Park, J., Larson, L., & Cauwenberghs, G. (2014). A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 227-230). Article 6942063 (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942063

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. / Kim, Chul; Ha, Sohmyung; Thomas, Chris et al.
ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. IEEE Computer Society, 2014. p. 227-230 6942063 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, C, Ha, S, Thomas, C, Joshi, S, Park, J, Larson, L & Cauwenberghs, G 2014, A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942063, European Solid-State Circuits Conference, IEEE Computer Society, pp. 227-230, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 9/22/14. https://doi.org/10.1109/ESSCIRC.2014.6942063

Kim C, Ha S, Thomas C, Joshi S, Park J, Larson L et al. A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. In Andreani P, Bevilacqua A, Meneghesso G, editors, ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 227-230. 6942063. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2014.6942063

Kim, Chul ; Ha, Sohmyung ; Thomas, Chris et al. / A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. editor / Pietro Andreani ; Andrea Bevilacqua ; Gaudenzio Meneghesso. IEEE Computer Society, 2014. pp. 227-230 (European Solid-State Circuits Conference).

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abstract = "We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3 of +12.5 dBm at 320 MHz LO over 3 MHz baseband. The 1.62mm2 mixer in 65nm CMOS consumes 40 μW per I/Q complex output channel, and 7.82 mW for 16-phase PLL clock generation and distribution.",

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A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS

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