TY - GEN
T1 - A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW
AU - Kim, Chul
AU - Joshi, Siddharth
AU - Thomas, Chris
AU - Ha, Sohmyung
AU - Akinin, Abraham
AU - Larson, Lawrence
AU - Cauwenberghs, Gert
N1 - Publisher Copyright:
© 2015 JSAP.
PY - 2015/8/31
Y1 - 2015/8/31
N2 - A CMOS integrated 4-channel capacitive harmonic rejection baseband receiver and 4x4 MIMO analog core spatial filter demonstrate >65dB harmonic folding rejection over 48MHz, and >48.5dB signal separation across 3MHz baseband. The 65nm CMOS IC occupies 3.27mm2 active area and consumes 0.67mW-1.28mW.
AB - A CMOS integrated 4-channel capacitive harmonic rejection baseband receiver and 4x4 MIMO analog core spatial filter demonstrate >65dB harmonic folding rejection over 48MHz, and >48.5dB signal separation across 3MHz baseband. The 65nm CMOS IC occupies 3.27mm2 active area and consumes 0.67mW-1.28mW.
UR - http://www.scopus.com/inward/record.url?scp=84957866495&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84957866495&partnerID=8YFLogxK
U2 - 10.1109/VLSIC.2015.7231300
DO - 10.1109/VLSIC.2015.7231300
M3 - Conference contribution
AN - SCOPUS:84957866495
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C304-C305
BT - 2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Y2 - 17 June 2015 through 19 June 2015
ER -