The advent of the multicore era [1, 2] has made the execution of more complex software applications more efficient and faster. On-chip communication among the processing cores, in the form of packetized messages, is managed with the use of on-chip networks (NoCs) . Routers handling on-chip communication are point-to-point topologically interconnected using parallel links laid onto the silicon surface comprising a number of individual parallel wires. With the underlying interconnect structure becoming denser, due to improvements in CMOS technology, parallel links become susceptible to wear-out , with permanent link failures inhibiting communication completely and indefinitely. It is hence critical to explore their failure patterns in the wires comprising these links and hence build mechanisms which can recover corrupted in-transit data [5, 6]; since no real data from chip manufacturers exist, the derivation of a mathematical model in aiding the understanding of the distribution of individual wire faults in parallel on-chip links becomes mandatory. This paper takes the first steps in such direction. First it is shown how the given problem reduces to an equivalent combinatorial problem through partitions and necklaces. Then a model that counts certain classes of necklaces is derived by making a separation between periodic and aperiodic cases. The model is tested against a brute-force algorithm to prove its exactness. Finally the obtained model is used in finding the probability distribution of the size of the fault segment of wires in a parallel NoC-based multicore chip.