Abstract
Editor's note: Testability is a perennial concern that requires ever-improved solutions; however, potentially resultant security vulnerabilities need to be considered as well. This article provides a compact look at a body of DfT work from lead practitioners in the field. The DfT strategies address predicting and controlling test data volume and reducing power. Potential impacts of DfT to security are considered, along with strategies for providing testability without sacrificing security.
Original language | English (US) |
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Article number | 7403884 |
Pages (from-to) | 57-64 |
Number of pages | 8 |
Journal | IEEE Design and Test |
Volume | 34 |
Issue number | 1 |
DOIs | |
State | Published - Feb 2017 |
Keywords
- Design-for-testability
- Hardware security
- Low power test
- Scan attack
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering