A constant array multiplier core generator with dynamic partial evaluation architecture selection

Bo Yang, Nikhil Joshi, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Numerous applications in Digital Signal Processing (DSP), telecommunications, graphics, cryptography and control systems have computations that involve a large number of multiplications of one variable with one or several constants. In this paper, we present a constant array multiplier core generator using dynamic partial evaluation. The proposed constant array multiplier core generator combines a new partial evaluation method named Full Complement Recoding with Booth's recoding and the straightforward partial evaluation method. Based on the number of 0s, the number of runs that have more than two consecutive 1s and the total number of 1s in all the runs in the constant operand, the proposed multiplier core generator selects one of the three partial evaluation methods to construct a partial evaluation architecture and generate an efficient Hardware Description Language (HDL) code that can be used as a design component. The constant multiplier core generated by the Xilinx CORE Generator™ system does not provide the optimized constant multipliers for a large number of cases. When implemented using Xilinx FPGA Virtex II device, the average area saving and delay improvement of the constant multiplier generated by proposed core generator is 70% and 36% compared to the 55% and 15% of constant multipliers generated by Xilinx CORE Generator™ system.

Original languageEnglish (US)
Title of host publicationACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
Pages280
Number of pages1
StatePublished - 2005
EventACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States
Duration: Feb 20 2005Feb 22 2005

Other

OtherACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
CountryUnited States
CityMonterey, CA
Period2/20/052/22/05

ASJC Scopus subject areas

  • Computer Science(all)

Fingerprint Dive into the research topics of 'A constant array multiplier core generator with dynamic partial evaluation architecture selection'. Together they form a unique fingerprint.

  • Cite this

    Yang, B., Joshi, N., & Karri, R. (2005). A constant array multiplier core generator with dynamic partial evaluation architecture selection. In ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 (pp. 280)