A deblocking filter hardware architecture for the high efficiency video coding standard

Claudio Machado Diniz, Muhammad Shafique, Felipe Vogel Dalcin, Sergio Bampi, Jorg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048@ 60 fps) with 5X-6X lower area compared to state-of-the-art deblocking filter architectures.

Original languageEnglish (US)
Title of host publicationProceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1509-1514
Number of pages6
ISBN (Electronic)9783981537048
DOIs
StatePublished - Apr 22 2015
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: Mar 9 2015Mar 13 2015

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume2015-April
ISSN (Print)1530-1591

Other

Other2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period3/9/153/13/15

Keywords

  • Deblocking Filter
  • Hardware Architecture
  • HEVC coding

ASJC Scopus subject areas

  • Engineering(all)

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