A deblocking filter hardware architecture for the high efficiency video coding standard

Claudio Machado Diniz; Muhammad Shafique; Felipe Vogel Dalcin; Sergio Bampi; Jorg Henkel

doi:10.7873/date.2015.0856

A deblocking filter hardware architecture for the high efficiency video coding standard

Claudio Machado Diniz, Muhammad Shafique, Felipe Vogel Dalcin, Sergio Bampi, Jorg Henkel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048@ 60 fps) with 5X-6X lower area compared to state-of-the-art deblocking filter architectures.

Original language	English (US)
Title of host publication	Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1509-1514
Number of pages	6
ISBN (Electronic)	9783981537048
DOIs	https://doi.org/10.7873/date.2015.0856
State	Published - Apr 22 2015
Event	2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France Duration: Mar 9 2015 → Mar 13 2015

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
Volume	2015-April
ISSN (Print)	1530-1591

Other

Other	2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Country/Territory	France
City	Grenoble
Period	3/9/15 → 3/13/15

Keywords

Deblocking Filter
Hardware Architecture
HEVC coding

ASJC Scopus subject areas

General Engineering

Access to Document

10.7873/date.2015.0856

Cite this

Diniz, C. M., Shafique, M., Dalcin, F. V., Bampi, S., & Henkel, J. (2015). A deblocking filter hardware architecture for the high efficiency video coding standard. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 (pp. 1509-1514). Article 7092628 (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.7873/date.2015.0856

A deblocking filter hardware architecture for the high efficiency video coding standard. / Diniz, Claudio Machado; Shafique, Muhammad; Dalcin, Felipe Vogel et al.
Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 1509-1514 7092628 (Proceedings -Design, Automation and Test in Europe, DATE; Vol. 2015-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Diniz, CM, Shafique, M, Dalcin, FV, Bampi, S & Henkel, J 2015, A deblocking filter hardware architecture for the high efficiency video coding standard. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015., 7092628, Proceedings -Design, Automation and Test in Europe, DATE, vol. 2015-April, Institute of Electrical and Electronics Engineers Inc., pp. 1509-1514, 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015, Grenoble, France, 3/9/15. https://doi.org/10.7873/date.2015.0856

Diniz CM, Shafique M, Dalcin FV, Bampi S, Henkel J. A deblocking filter hardware architecture for the high efficiency video coding standard. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 1509-1514. 7092628. (Proceedings -Design, Automation and Test in Europe, DATE). doi: 10.7873/date.2015.0856

Diniz, Claudio Machado ; Shafique, Muhammad ; Dalcin, Felipe Vogel et al. / A deblocking filter hardware architecture for the high efficiency video coding standard. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 1509-1514 (Proceedings -Design, Automation and Test in Europe, DATE).

@inproceedings{69947ba3fbf14dc6a2a3e4fae2f08f05,

title = "A deblocking filter hardware architecture for the high efficiency video coding standard",

abstract = "The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048@ 60 fps) with 5X-6X lower area compared to state-of-the-art deblocking filter architectures.",

keywords = "Deblocking Filter, Hardware Architecture, HEVC coding",

author = "Diniz, {Claudio Machado} and Muhammad Shafique and Dalcin, {Felipe Vogel} and Sergio Bampi and Jorg Henkel",

note = "Publisher Copyright: {\textcopyright} 2015 EDAA. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.; 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 ; Conference date: 09-03-2015 Through 13-03-2015",

year = "2015",

month = apr,

day = "22",

doi = "10.7873/date.2015.0856",

language = "English (US)",

series = "Proceedings -Design, Automation and Test in Europe, DATE",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1509--1514",

booktitle = "Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015",

}

TY - GEN

T1 - A deblocking filter hardware architecture for the high efficiency video coding standard

AU - Diniz, Claudio Machado

AU - Shafique, Muhammad

AU - Dalcin, Felipe Vogel

AU - Bampi, Sergio

AU - Henkel, Jorg

PY - 2015/4/22

Y1 - 2015/4/22

N2 - The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048@ 60 fps) with 5X-6X lower area compared to state-of-the-art deblocking filter architectures.

AB - The new deblocking filter (DF) tool of the next generation High Efficiency Video Coding (HEVC) standard is one of the most time consuming algorithms in video decoding. In order to achieve real-time performance at low-power consumption, we developed a hardware accelerator for this filter. This paper proposes a high throughput hardware architecture for HEVC deblocking filter employing hardware reuse to accelerate filtering decision units with a low area cost. Our architecture achieves either higher or equivalent throughput (4096×2048@ 60 fps) with 5X-6X lower area compared to state-of-the-art deblocking filter architectures.

KW - Deblocking Filter

KW - Hardware Architecture

KW - HEVC coding

UR - http://www.scopus.com/inward/record.url?scp=84945893923&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84945893923&partnerID=8YFLogxK

U2 - 10.7873/date.2015.0856

DO - 10.7873/date.2015.0856

M3 - Conference contribution

AN - SCOPUS:84945893923

T3 - Proceedings -Design, Automation and Test in Europe, DATE

SP - 1509

EP - 1514

BT - Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015

Y2 - 9 March 2015 through 13 March 2015

ER -

A deblocking filter hardware architecture for the high efficiency video coding standard

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this