A design methodology for the high-level synthesis of fault-tolerant ASICs

Alex Orailoǧlu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Increased levels of integration are leading to single-chip systems and on-chip fault-tolerance. Whereas methodologies for designing fault-tolerant systems have been well understood, software mechanisms for the automatic synthesis of fault-tolerant application specific ICs (ASICs) remain relatively unexplored. In this paper, we systematically explore the three-dimensional design space spanned by cost, performance, and fault-tolerance constraints. In particular, we propose synthesis methodologies to (i) minimize cost subject to performance and fault-tolerance constraints, and (ii) maximize fault-tolerance given cost and performance constraints.

Original languageEnglish (US)
Title of host publicationWorkshop on VLSI Signal Processing 1992
EditorsWojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages417-426
Number of pages10
ISBN (Electronic)0780308115, 9780780308114
DOIs
StatePublished - 1992
Event6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States
Duration: Oct 28 1992Oct 30 1992

Publication series

NameWorkshop on VLSI Signal Processing 1992

Conference

Conference6th IEEE Workshop on VLSI Signal Processing
CountryUnited States
CityLos Angeles
Period10/28/9210/30/92

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering
  • Applied Mathematics

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    Orailoǧlu, A., & Karri, R. (1992). A design methodology for the high-level synthesis of fault-tolerant ASICs. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 417-426). [641073] (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641073