A design methodology for the high-level synthesis of fault-tolerant ASICs

Alex Orailoǧlu; Ramesh Karri

doi:10.1109/VLSISP.1992.641073

A design methodology for the high-level synthesis of fault-tolerant ASICs

Alex Orailoǧlu, Ramesh Karri

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Increased levels of integration are leading to single-chip systems and on-chip fault-tolerance. Whereas methodologies for designing fault-tolerant systems have been well understood, software mechanisms for the automatic synthesis of fault-tolerant application specific ICs (ASICs) remain relatively unexplored. In this paper, we systematically explore the three-dimensional design space spanned by cost, performance, and fault-tolerance constraints. In particular, we propose synthesis methodologies to (i) minimize cost subject to performance and fault-tolerance constraints, and (ii) maximize fault-tolerance given cost and performance constraints.

Original language	English (US)
Title of host publication	Workshop on VLSI Signal Processing 1992
Editors	Wojtek Przytula, Kung Yao, Rajeev Jain, Jan Rabaey
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	417-426
Number of pages	10
ISBN (Electronic)	0780308115, 9780780308114
DOIs	https://doi.org/10.1109/VLSISP.1992.641073
State	Published - 1992
Event	6th IEEE Workshop on VLSI Signal Processing - Los Angeles, United States Duration: Oct 28 1992 → Oct 30 1992

Publication series

Name	Workshop on VLSI Signal Processing 1992

Conference

Conference	6th IEEE Workshop on VLSI Signal Processing
Country/Territory	United States
City	Los Angeles
Period	10/28/92 → 10/30/92

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Applied Mathematics

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10.1109/VLSISP.1992.641073

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Orailoǧlu, A., & Karri, R. (1992). A design methodology for the high-level synthesis of fault-tolerant ASICs. In W. Przytula, K. Yao, R. Jain, & J. Rabaey (Eds.), Workshop on VLSI Signal Processing 1992 (pp. 417-426). Article 641073 (Workshop on VLSI Signal Processing 1992). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSISP.1992.641073

A design methodology for the high-level synthesis of fault-tolerant ASICs. / Orailoǧlu, Alex; Karri, Ramesh.
Workshop on VLSI Signal Processing 1992. ed. / Wojtek Przytula; Kung Yao; Rajeev Jain; Jan Rabaey. Institute of Electrical and Electronics Engineers Inc., 1992. p. 417-426 641073 (Workshop on VLSI Signal Processing 1992).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Orailoǧlu, A & Karri, R 1992, A design methodology for the high-level synthesis of fault-tolerant ASICs. in W Przytula, K Yao, R Jain & J Rabaey (eds), Workshop on VLSI Signal Processing 1992., 641073, Workshop on VLSI Signal Processing 1992, Institute of Electrical and Electronics Engineers Inc., pp. 417-426, 6th IEEE Workshop on VLSI Signal Processing, Los Angeles, United States, 10/28/92. https://doi.org/10.1109/VLSISP.1992.641073

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A design methodology for the high-level synthesis of fault-tolerant ASICs

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