TY - GEN
T1 - A design space exploration methodology for parameter optimization in multicore processors
AU - Kansakar, Prasanna
AU - Munir, Arslan
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/9/2
Y1 - 2016/9/2
N2 - Due to the increasing proliferation of computing systems in diverse application domains, the need for application-specific design of multicore/manycore processing platforms is paramount. In order to tailor processors for application-specific requirements, a multitude of processor design parameters need to be tuned accordingly. Tuning of processor design parameters involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient design space exploration methodology for multicore parameter optimization. Our proposed methodology includes an intelligent initial parameter setting algorithm, the results of which are leveraged by two search algorithms - exhaustive search and greedy search. We evaluate the methodology in a cycle-accurate simulator (ESESC) using standard set of PARSEC and SPLASH2 benchmarks for applications with low-power and high-performance requirements. The results reveal that the quality of solutions (design configurations) obtained from our methodology are within 1.35%-3.69% of the solutions obtained from fully exhaustive search while only exploring 2.74%-3% of the design space. Our methodology achieves on average a 35.32x speedup in design space exploration time as compared to fully exhaustive search in finding the best processor design configuration.
AB - Due to the increasing proliferation of computing systems in diverse application domains, the need for application-specific design of multicore/manycore processing platforms is paramount. In order to tailor processors for application-specific requirements, a multitude of processor design parameters need to be tuned accordingly. Tuning of processor design parameters involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient design space exploration methodology for multicore parameter optimization. Our proposed methodology includes an intelligent initial parameter setting algorithm, the results of which are leveraged by two search algorithms - exhaustive search and greedy search. We evaluate the methodology in a cycle-accurate simulator (ESESC) using standard set of PARSEC and SPLASH2 benchmarks for applications with low-power and high-performance requirements. The results reveal that the quality of solutions (design configurations) obtained from our methodology are within 1.35%-3.69% of the solutions obtained from fully exhaustive search while only exploring 2.74%-3% of the design space. Our methodology achieves on average a 35.32x speedup in design space exploration time as compared to fully exhaustive search in finding the best processor design configuration.
KW - design space exploration
KW - multicore/manycore processors
KW - parameter optimization
KW - processor design parameters
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U2 - 10.1109/ISVLSI.2016.92
DO - 10.1109/ISVLSI.2016.92
M3 - Conference contribution
AN - SCOPUS:84988939478
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 613
EP - 618
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
PB - IEEE Computer Society
T2 - 15th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016
Y2 - 11 July 2016 through 13 July 2016
ER -