TY - GEN
T1 - A Fine-Grained Soft Error Resilient Architecture under Power Considerations
AU - Hussain, Sajjad
AU - Shafique, Muhammad
AU - Henkel, Jörg
N1 - Funding Information:
ACKNOWLEDGEMENT This work is supported in parts by the German Research Foundation (DFG) as part of the priority program "Dependable Embedded Systems" (SPP 1500 - spp1500.itec.kit.edu).
Publisher Copyright:
© 2019 EDAA.
Copyright:
Copyright 2019 Elsevier B.V., All rights reserved.
PY - 2019/5/14
Y1 - 2019/5/14
N2 - Besides the limited power budgets and the darksilicon issue, soft error is one of the most critical reliability issues in computing systems fabricated using nano-scale devices. During the execution, different applications have varying performance, power/energy consumption and vulnerability properties. Different trade-offs can be devised to provide required resiliency within the allowed power constraints. To exploit this behavior, we propose a novel soft error resilient architecture and the corresponding run-time system that enables power-aware finegrained resiliency for different processor components. It selectively determines the reliability state of various components, such that the overall application reliability is improved under a given power budget. Our architecture saves power up to 16% and reliability degradation up to 11% compared to state-of-the-art techniques.
AB - Besides the limited power budgets and the darksilicon issue, soft error is one of the most critical reliability issues in computing systems fabricated using nano-scale devices. During the execution, different applications have varying performance, power/energy consumption and vulnerability properties. Different trade-offs can be devised to provide required resiliency within the allowed power constraints. To exploit this behavior, we propose a novel soft error resilient architecture and the corresponding run-time system that enables power-aware finegrained resiliency for different processor components. It selectively determines the reliability state of various components, such that the overall application reliability is improved under a given power budget. Our architecture saves power up to 16% and reliability degradation up to 11% compared to state-of-the-art techniques.
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U2 - 10.23919/DATE.2019.8714797
DO - 10.23919/DATE.2019.8714797
M3 - Conference contribution
AN - SCOPUS:85066602922
T3 - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
SP - 972
EP - 975
BT - Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
Y2 - 25 March 2019 through 29 March 2019
ER -