Abstract
Signaling protocols in switches are primarily implemented in software for two important reasons. First, signaling protocols are quite complex with many messages, parameters and procedures. Second, signaling protocols are updated frequently requiring a certain amount of flexibility for upgrading field implementations. While these are two good reasons for implementing signaling protocols in software, there is an associated performance penalty. Even with state-of-the-art processors, software implementations of signaling protocol are rarely capable of handling over 1000 calls/sec. Correspondingly, call setup delays per switch are in the order of milliseconds. Towards improving performance we implemented a signaling protocol in reconfigurable FPGA hardware. Our implementation demonstrates the feasibility of 100x-1000x speedup vis-à-vis software implementations on state-of-the-art processors. The impact of this work can be quite far-reaching by allowing connection-oriented networks to support a variety of new applications, even those with short call holding times.
Original language | English (US) |
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Title of host publication | Proceedings of SPIE - The International Society for Optical Engineering |
Editors | N. Ghani, K.M. Sivalingam |
Pages | 174-185 |
Number of pages | 12 |
Volume | 4874 |
DOIs | |
State | Published - 2002 |
Event | OptiComn 2002 Optical Networking and Communications - Boston, MA, United States Duration: Jul 30 2002 → Jul 31 2002 |
Other
Other | OptiComn 2002 Optical Networking and Communications |
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Country/Territory | United States |
City | Boston, MA |
Period | 7/30/02 → 7/31/02 |
Keywords
- FPGA
- GMPLS
- Hardware acceleration
- Signaling protocols
- SONET/SDH
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Condensed Matter Physics