A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding

Muhammad Shafique; Adnan Orçun Tüfek; Jörg Henkel

doi:10.1109/ICIP.2011.6116532

A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding

Muhammad Shafique, Adnan Orçun Tüfek, Jörg Henkel

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of-the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4x4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2x higher throughput, while processing HD1080p@30fps.

Original language	English (US)
Title of host publication	ICIP 2011
Subtitle of host publication	2011 18th IEEE International Conference on Image Processing
Pages	393-396
Number of pages	4
DOIs	https://doi.org/10.1109/ICIP.2011.6116532
State	Published - 2011
Event	2011 18th IEEE International Conference on Image Processing, ICIP 2011 - Brussels, Belgium Duration: Sep 11 2011 → Sep 14 2011

Publication series

Name	Proceedings - International Conference on Image Processing, ICIP
ISSN (Print)	1522-4880

Other

Other	2011 18th IEEE International Conference on Image Processing, ICIP 2011
Country	Belgium
City	Brussels
Period	9/11/11 → 9/14/11

Keywords

Entropy Coding
H.264/AVC
Hardware Architecture

ASJC Scopus subject areas

Software
Computer Vision and Pattern Recognition
Signal Processing

Access to Document

10.1109/ICIP.2011.6116532

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A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding. / Shafique, Muhammad; Tüfek, Adnan Orçun; Henkel, Jörg.

ICIP 2011: 2011 18th IEEE International Conference on Image Processing. 2011. p. 393-396 6116532 (Proceedings - International Conference on Image Processing, ICIP).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shafique, M, Tüfek, AO & Henkel, J 2011, A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding. in ICIP 2011: 2011 18th IEEE International Conference on Image Processing., 6116532, Proceedings - International Conference on Image Processing, ICIP, pp. 393-396, 2011 18th IEEE International Conference on Image Processing, ICIP 2011, Brussels, Belgium, 9/11/11. https://doi.org/10.1109/ICIP.2011.6116532

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