A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding

Muhammad Shafique, Adnan Orçun Tüfek, Jörg Henkel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of-the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4x4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2x higher throughput, while processing HD1080p@30fps.

Original languageEnglish (US)
Title of host publicationICIP 2011
Subtitle of host publication2011 18th IEEE International Conference on Image Processing
Pages393-396
Number of pages4
DOIs
StatePublished - 2011
Event2011 18th IEEE International Conference on Image Processing, ICIP 2011 - Brussels, Belgium
Duration: Sep 11 2011Sep 14 2011

Publication series

NameProceedings - International Conference on Image Processing, ICIP
ISSN (Print)1522-4880

Other

Other2011 18th IEEE International Conference on Image Processing, ICIP 2011
CountryBelgium
CityBrussels
Period9/11/119/14/11

Keywords

  • Entropy Coding
  • H.264/AVC
  • Hardware Architecture

ASJC Scopus subject areas

  • Software
  • Computer Vision and Pattern Recognition
  • Signal Processing

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