TY - GEN
T1 - A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding
AU - Shafique, Muhammad
AU - Tüfek, Adnan Orçun
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2011
Y1 - 2011
N2 - This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of-the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4x4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2x higher throughput, while processing HD1080p@30fps.
AB - This paper presents a high-throughput hardware architecture for H.264/AVC CAVLC encoding. Our scheme eliminates the pipeline stage of computing the coefficient statistics (as adopted by state-of-the-art hardware architectures) with a pre-processing stage during the quantization in order to avoid the extra looping logic in CAVLC. This provides significant performance improvement compared to state-of-the-art (saving of 16 cycles per 4x4 sub-block compared to [2]). Furthermore, our hardware architecture employs parallel processing of Trailing Ones (which is one of the inherently sequential steps in CAVLC) and encodes levels and runs in parallel in the same pipeline stage. An intelligent bitstream writing logic generates the compliant bitstream. Compared to state-of-the-art, our proposed hardware architecture requires 72% reduced area and achieves 2x higher throughput, while processing HD1080p@30fps.
KW - Entropy Coding
KW - H.264/AVC
KW - Hardware Architecture
UR - http://www.scopus.com/inward/record.url?scp=84856259574&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84856259574&partnerID=8YFLogxK
U2 - 10.1109/ICIP.2011.6116532
DO - 10.1109/ICIP.2011.6116532
M3 - Conference contribution
AN - SCOPUS:84856259574
SN - 9781457713033
T3 - Proceedings - International Conference on Image Processing, ICIP
SP - 393
EP - 396
BT - ICIP 2011
T2 - 2011 18th IEEE International Conference on Image Processing, ICIP 2011
Y2 - 11 September 2011 through 14 September 2011
ER -