TY - GEN
T1 - A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting
AU - Vitkovskiy, Arseniy
AU - Soteriou, Vassos
AU - Nicopoulos, Chrysostomos
PY - 2012
Y1 - 2012
N2 - Denser transistor integration has enabled the fabrication of multi-tile chips, however, at the expense of higher susceptibility to defects and wear-out. Metal wires comprising the links of Networks-on-Chip (NoCs) are especially vulnerable to such defects, which can render some links disconnected. This paper presents a new fault-tolerant routing scheme to sustain on-chip communication. It uses a localized re-routing approach, whereby de-touring around faulty links - or complex regions of faults - is done locally at each node in a purely distributed and dynamic manner, while guaranteeing deadlock- and livelock-freedom. Results using synthetic traffic and real applications with full-system simulations prove its efficacy in addressing a large percentage of NoC links being faulty albeit at a gracefully degraded performance mode.
AB - Denser transistor integration has enabled the fabrication of multi-tile chips, however, at the expense of higher susceptibility to defects and wear-out. Metal wires comprising the links of Networks-on-Chip (NoCs) are especially vulnerable to such defects, which can render some links disconnected. This paper presents a new fault-tolerant routing scheme to sustain on-chip communication. It uses a localized re-routing approach, whereby de-touring around faulty links - or complex regions of faults - is done locally at each node in a purely distributed and dynamic manner, while guaranteeing deadlock- and livelock-freedom. Results using synthetic traffic and real applications with full-system simulations prove its efficacy in addressing a large percentage of NoC links being faulty albeit at a gracefully degraded performance mode.
KW - fault-tolerance
KW - on-chip networks
KW - routing algorithm
UR - http://www.scopus.com/inward/record.url?scp=84856945737&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84856945737&partnerID=8YFLogxK
U2 - 10.1145/2107763.2107771
DO - 10.1145/2107763.2107771
M3 - Conference contribution
AN - SCOPUS:84856945737
SN - 9781450310109
T3 - ACM International Conference Proceeding Series
SP - 29
EP - 32
BT - Proceedings of the 2012 Interconnection Network Architecture
T2 - 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop, INA-OCMC'12
Y2 - 25 January 2012 through 25 January 2012
ER -