A lateral structure for low-cost fabrication of COOLMOS™ on SOI wafers is proposed and the feasibility of the fabrication steps is verified by simulation in GENESISe environment. The requirement of multiple epitaxy and implantation steps for the growth of voltage-sustaining pillars in conventional vertical COOLMOS™ is automatically eliminated in the proposed method through the use of the lateral structure fabricated on SOI wafer. DESSIS simulations confirm the functionality of the proposed device, including the so-called quasi-saturation effect. In addition to the successful transistor behaviour of the lateral COOLMOS™, the proposed fabrication method has the advantage of low-cost processing steps in comparison with the conventional vertical fabrication approach, and also offers compatibility for on-chip integration with CMOS control circuitry.
- On-chip realization
- Power transistor
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry