A lateral structure for low-cost fabrication of COOLMOS™

Davood Shahrjerdi; Morteza Fathipour; Bahman Hekmatshoar; Ali Khakifirooz

doi:10.1016/j.sse.2004.05.041

A lateral structure for low-cost fabrication of COOLMOS™

Davood Shahrjerdi, Morteza Fathipour, Bahman Hekmatshoar, Ali Khakifirooz

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A lateral structure for low-cost fabrication of COOLMOS™ on SOI wafers is proposed and the feasibility of the fabrication steps is verified by simulation in GENESISe environment. The requirement of multiple epitaxy and implantation steps for the growth of voltage-sustaining pillars in conventional vertical COOLMOS™ is automatically eliminated in the proposed method through the use of the lateral structure fabricated on SOI wafer. DESSIS simulations confirm the functionality of the proposed device, including the so-called quasi-saturation effect. In addition to the successful transistor behaviour of the lateral COOLMOS™, the proposed fabrication method has the advantage of low-cost processing steps in comparison with the conventional vertical fabrication approach, and also offers compatibility for on-chip integration with CMOS control circuitry.

Original language	English (US)
Pages (from-to)	1953-1957
Number of pages	5
Journal	Solid-State Electronics
Volume	48
Issue number	10-11 SPEC. ISS.
DOIs	https://doi.org/10.1016/j.sse.2004.05.041
State	Published - Oct 2004

Keywords

COOLMOS™
On-chip realization
Power transistor
SOI

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1016/j.sse.2004.05.041

Cite this

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title = "A lateral structure for low-cost fabrication of COOLMOS{\texttrademark}",

abstract = "A lateral structure for low-cost fabrication of COOLMOS{\texttrademark} on SOI wafers is proposed and the feasibility of the fabrication steps is verified by simulation in GENESISe environment. The requirement of multiple epitaxy and implantation steps for the growth of voltage-sustaining pillars in conventional vertical COOLMOS{\texttrademark} is automatically eliminated in the proposed method through the use of the lateral structure fabricated on SOI wafer. DESSIS simulations confirm the functionality of the proposed device, including the so-called quasi-saturation effect. In addition to the successful transistor behaviour of the lateral COOLMOS{\texttrademark}, the proposed fabrication method has the advantage of low-cost processing steps in comparison with the conventional vertical fabrication approach, and also offers compatibility for on-chip integration with CMOS control circuitry.",

keywords = "COOLMOS{\texttrademark}, On-chip realization, Power transistor, SOI",

author = "Davood Shahrjerdi and Morteza Fathipour and Bahman Hekmatshoar and Ali Khakifirooz",

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AU - Shahrjerdi, Davood

AU - Fathipour, Morteza

AU - Hekmatshoar, Bahman

AU - Khakifirooz, Ali

PY - 2004/10

Y1 - 2004/10

N2 - A lateral structure for low-cost fabrication of COOLMOS™ on SOI wafers is proposed and the feasibility of the fabrication steps is verified by simulation in GENESISe environment. The requirement of multiple epitaxy and implantation steps for the growth of voltage-sustaining pillars in conventional vertical COOLMOS™ is automatically eliminated in the proposed method through the use of the lateral structure fabricated on SOI wafer. DESSIS simulations confirm the functionality of the proposed device, including the so-called quasi-saturation effect. In addition to the successful transistor behaviour of the lateral COOLMOS™, the proposed fabrication method has the advantage of low-cost processing steps in comparison with the conventional vertical fabrication approach, and also offers compatibility for on-chip integration with CMOS control circuitry.

AB - A lateral structure for low-cost fabrication of COOLMOS™ on SOI wafers is proposed and the feasibility of the fabrication steps is verified by simulation in GENESISe environment. The requirement of multiple epitaxy and implantation steps for the growth of voltage-sustaining pillars in conventional vertical COOLMOS™ is automatically eliminated in the proposed method through the use of the lateral structure fabricated on SOI wafer. DESSIS simulations confirm the functionality of the proposed device, including the so-called quasi-saturation effect. In addition to the successful transistor behaviour of the lateral COOLMOS™, the proposed fabrication method has the advantage of low-cost processing steps in comparison with the conventional vertical fabrication approach, and also offers compatibility for on-chip integration with CMOS control circuitry.

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KW - On-chip realization

KW - Power transistor

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A lateral structure for low-cost fabrication of COOLMOS™

Abstract

Keywords

ASJC Scopus subject areas

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