TY - GEN
T1 - A low latency generic accuracy configurable adder
AU - Shafique, Muhammad
AU - Ahmad, Waqas
AU - Hafiz, Rehan
AU - Henkel, Jörg
N1 - Publisher Copyright:
© 2015 ACM.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2015/7/24
Y1 - 2015/7/24
N2 - High performance approximate adders typically comprise of multIPle smaller sub-adders, carry prediction units and error correction units. In this paper, we present a low-latency generic accuracy configurable adder to support variable approximation modes. It provides a higher number of potential configurations compared to state-of-the-art, thus enabling a high degree of design flexibility and trade-off between performance and output quality. An error correction unit is integrated to provide accurate results for cases where high accuracy is required. Furthermore, an associated scheme for error probability estimation allows convenient comparison of different approximate adder configurations without requiring the need to numerically simulate the adder. Our experimental results validate the developed error model and also the lower latency of our generic accuracy configurable adder over state-of-the-art approximate adders. For functional verification and prototyping, we have used a Xilinx Virtex-6 FPGA. Our adder model and synthesizable RTL are made open-source.
AB - High performance approximate adders typically comprise of multIPle smaller sub-adders, carry prediction units and error correction units. In this paper, we present a low-latency generic accuracy configurable adder to support variable approximation modes. It provides a higher number of potential configurations compared to state-of-the-art, thus enabling a high degree of design flexibility and trade-off between performance and output quality. An error correction unit is integrated to provide accurate results for cases where high accuracy is required. Furthermore, an associated scheme for error probability estimation allows convenient comparison of different approximate adder configurations without requiring the need to numerically simulate the adder. Our experimental results validate the developed error model and also the lower latency of our generic accuracy configurable adder over state-of-the-art approximate adders. For functional verification and prototyping, we have used a Xilinx Virtex-6 FPGA. Our adder model and synthesizable RTL are made open-source.
KW - Adder
KW - Approximate Computing
KW - Arithmetic
KW - Configurable Accuracy
KW - Performance
UR - http://www.scopus.com/inward/record.url?scp=84944088465&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84944088465&partnerID=8YFLogxK
U2 - 10.1145/2744769.2744778
DO - 10.1145/2744769.2744778
M3 - Conference contribution
AN - SCOPUS:84944088465
T3 - Proceedings - Design Automation Conference
BT - 2015 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 52nd ACM/EDAC/IEEE Design Automation Conference, DAC 2015
Y2 - 8 June 2015 through 12 June 2015
ER -