TY - GEN
T1 - A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding
AU - Zatt, Bruno
AU - Shafique, Muhammad
AU - Bampi, Sergio
AU - Henkel, Jörg
N1 - Copyright:
Copyright 2012 Elsevier B.V., All rights reserved.
PY - 2011
Y1 - 2011
N2 - A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.
AB - A low-power architecture for an on-chip multi-banked video memory for motion and disparity estimation in Multiview Video Coding is proposed. The memory organization (size, banks, sectors, etc.) is driven by an extensive analysis of memory-usage behavior for various 3D-video sequences. Considering a multiple-sleep state model, an application-aware power management scheme is employed to reduce the leakage energy of the on-chip memory. The knowledge of motion and disparity estimation algorithm in conjunction with video properties are considered to predict the memory requirements of each Macroblock. A cost function is evaluated to determine an appropriate sleep mode for the idle memory sectors, while considering the wakeup overhead (latency and energy). The complete motion and disparity estimation architecture is implemented in a 65nm low power IBM technology. The experiments (for various test video sequences) demonstrate that our architecture provides up to 80% leakage energy reduction compared to state-of-the-art. Our scheme processes motion and disparity estimation of four HD1080p views encoding at 30fps with a power consumption of 57mW.
KW - application-aware power management
KW - disparity estimation
KW - low power
KW - motion estimation
KW - Multiview video coding
KW - on-chip memory
KW - power-gating
KW - video memory
UR - http://www.scopus.com/inward/record.url?scp=84855814161&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84855814161&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2011.6105303
DO - 10.1109/ICCAD.2011.6105303
M3 - Conference contribution
AN - SCOPUS:84855814161
SN - 9781457713989
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 40
EP - 47
BT - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
T2 - 2011 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2011
Y2 - 7 November 2011 through 10 November 2011
ER -