TY - GEN
T1 - A non-intrusive isolation approach for soft cores
AU - Sinanoglu, Ozgur
AU - Petrov, Tsvetomir
PY - 2007
Y1 - 2007
N2 - Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. In this paper, we propose a non-intrusive core isolation technique that is based on the utilization of existing core registers for isolating the core. We provide a core register partitioning algorithm that is capable of identifying the core interface registers, and of robustly isolating a core, resulting in a computationally efficient core isolation implementation that is area and performance efficient at the same time. The proposed isolation technique also ensures minimal test time increase and no at-speed coverage loss on the core interface, offering an elegant solution for soft cores, and thus enabling significant SOC test cost reductions.
AB - Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. In this paper, we propose a non-intrusive core isolation technique that is based on the utilization of existing core registers for isolating the core. We provide a core register partitioning algorithm that is capable of identifying the core interface registers, and of robustly isolating a core, resulting in a computationally efficient core isolation implementation that is area and performance efficient at the same time. The proposed isolation technique also ensures minimal test time increase and no at-speed coverage loss on the core interface, offering an elegant solution for soft cores, and thus enabling significant SOC test cost reductions.
UR - http://www.scopus.com/inward/record.url?scp=34548295449&partnerID=8YFLogxK
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U2 - 10.1109/DATE.2007.364562
DO - 10.1109/DATE.2007.364562
M3 - Conference contribution
AN - SCOPUS:34548295449
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 27
EP - 32
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -