A petabit photonic packet switch (P3S)

H. Jonathan Chao, Kung Li Deng, Zhigang Jing

Research output: Contribution to journalConference articlepeer-review


This paper presents a new petabit photonic packet switch (P3S) architecture that is highly scalable both in dimension and capacity while maintaining high system performances. Using a new multi-dimensional photonic multiplexing scheme that includes space, time, wavelength, and sub-carrier domains, we propose a photonic switch fabric based on a 3-stage Clos network to provide scalable large-dimension photonic interconnections with nanosecond reconfiguration speed. Packet buffering is implemented electronically at the input and output port controllers, allowing the central photonic switch fabric to transport high-speed optical signals without electrical-to-optical conversion. Optical time division multiplexing (OTDM) technology further scales port speed beyond electronic speed up to 160 Gbits/s to minimize the fiber connections. To solve output contention, we propose a new arbitration scheme, called Frame-based Exhaustive Matching (FEM), using extended frames to aggregate cells from different incoming lines. The extended frame relaxes the stringent arbitration time constraint at a 160 Gbit/s port speed. Based on the FEM scheme in the proposed architecture, a 6400 × 6400 switch with a total capacity of 1.024 petabit/s can be achieved with throughput close to 100% under various traffic conditions.

Original languageEnglish (US)
Pages (from-to)775-785
Number of pages11
JournalProceedings - IEEE INFOCOM
StatePublished - 2003
Event22nd Annual Joint Conference on the IEEE Computer and Communications Societies - San Francisco, CA, United States
Duration: Mar 30 2003Apr 3 2003


  • Clos network
  • Optical Time Division Multiplexing (OTDM)
  • Photonic switch
  • Scheduling

ASJC Scopus subject areas

  • General Computer Science
  • Electrical and Electronic Engineering


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