A reconfigurable hardware architecture for fractional pixel interpolation in high efficiency video coding

Cláudio M. Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel

Research output: Contribution to journalArticlepeer-review

Abstract

We present a novel reconfigurable hardware architecture for interpolation filtering in high efficient video coding that adapts to run-time changes of the number of interpolation filter calls and thereby provides a high potential of energy efficiency. It employs a picture-based prediction scheme to estimate the number of interpolation filter calls at run-time by monitoring the group of pictures history based on video coding structure knowledge. Reconfigurable acceleration engines are developed that can adapt to different filter types. Dynamic composition of different instances of these engines enables different implementation versions with area versus throughput tradeoff. A run-time selection scheme determines the best implementation version for each picture based on the throughput requirements. Compared to state-of-the-art, our architecture reduces resource usage by 57% while supporting various throughputs and video resolutions.

Original languageEnglish (US)
Article number6994230
Pages (from-to)238-251
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume34
Issue number2
DOIs
StatePublished - Feb 1 2015

Keywords

  • Accelerators
  • hardware architecture
  • high efficient video coding (HEVC)
  • interpolation filter
  • reconfigurable data paths

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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