TY - GEN
T1 - A secure design-for-test infrastructure for lifetime security of SoCs
AU - Backer, Jerry
AU - Ali, Sk Subidh
AU - Rosenfeld, Kurt
AU - Hely, David
AU - Sinanoglu, Ozgur
AU - Karri, Ramesh
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/7/27
Y1 - 2015/7/27
N2 - Modular design of a system-on-chip (SoC) exposes intellectual property (IP) and SoC assets to attacks in test, debug, and functional modes. We enhance the SoC Design-for-Test (DFT) infrastructure with security countermeasures to thwart these attacks. We first secure IP and SoC assets from attacks in test and debug modes, then reuse the DFT infrastructure to detect attacks in functional mode.
AB - Modular design of a system-on-chip (SoC) exposes intellectual property (IP) and SoC assets to attacks in test, debug, and functional modes. We enhance the SoC Design-for-Test (DFT) infrastructure with security countermeasures to thwart these attacks. We first secure IP and SoC assets from attacks in test and debug modes, then reuse the DFT infrastructure to detect attacks in functional mode.
UR - http://www.scopus.com/inward/record.url?scp=84946217224&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84946217224&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7168564
DO - 10.1109/ISCAS.2015.7168564
M3 - Conference contribution
AN - SCOPUS:84946217224
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 37
EP - 40
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -