A secure design-for-test infrastructure for lifetime security of SoCs

Jerry Backer, Sk Subidh Ali, Kurt Rosenfeld, David Hely, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Modular design of a system-on-chip (SoC) exposes intellectual property (IP) and SoC assets to attacks in test, debug, and functional modes. We enhance the SoC Design-for-Test (DFT) infrastructure with security countermeasures to thwart these attacks. We first secure IP and SoC assets from attacks in test and debug modes, then reuse the DFT infrastructure to detect attacks in functional mode.

Original languageEnglish (US)
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages37-40
Number of pages4
ISBN (Electronic)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period5/24/155/27/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Backer, J., Ali, S. S., Rosenfeld, K., Hely, D., Sinanoglu, O., & Karri, R. (2015). A secure design-for-test infrastructure for lifetime security of SoCs. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015 (pp. 37-40). [7168564] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2015-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2015.7168564