TY - GEN
T1 - A super-quadratic lower bound for depth four arithmetic circuits
AU - Gupta, Nikhil
AU - Saha, Chandan
AU - Thankey, Bhargav
N1 - Funding Information:
We would like to thank Neeraj Kayal and Ankit Garg for sitting through a presentation of this work and giving us useful feedback. Thanks specially to Ankit for bringing the work of Chen and Tell [20] to our notice. A part of this work is done at Microsoft Research India (MSRI), where CS is spending a sabbatical year. CS would like to thank MSRI for providing an excellent research environment and for the hospitality.
Publisher Copyright:
© Nikhil Gupta, Chandan Saha, and Bhargav Thankey; licensed under Creative Commons License CC-BY 35th Computational Complexity Conference (CCC 2020).
PY - 2020/7/1
Y1 - 2020/7/1
N2 - We show an Ω(e n2.5) lower bound for general depth four arithmetic circuits computing an explicit n-variate degree-Θ(n) multilinear polynomial over any field of characteristic zero. To our knowledge, and as stated in the survey [88], no super-quadratic lower bound was known for depth four circuits over fields of characteristic 6= 2 before this work. The previous best lower bound is Ω(e n1.5) [85], which is a slight quantitative improvement over the roughly Ω(n1.33) bound obtained by invoking the super-linear lower bound for constant depth circuits in [73,86]. Our lower bound proof follows the approach of the almost cubic lower bound for depth three circuits in [53] by replacing the shifted partials measure with a suitable variant of the projected shifted partials measure, but it differs from [53]'s proof at a crucial step - namely, the way “heavy” product gates are handled. Loosely speaking, a heavy product gate has a relatively high fan-in. Product gates of a depth three circuit compute products of affine forms, and so, it is easy to prune Θ(n) many heavy product gates by projecting the circuit to a low-dimensional affine subspace [53,87]. However, in a depth four circuit, the second (from the top) layer of product gates compute products of polynomials having arbitrary degree, and hence it was not clear how to prune such heavy product gates from the circuit. We show that heavy product gates can also be eliminated from a depth four circuit by projecting the circuit to a low-dimensional affine subspace, unless the heavy gates together account for Ω(e n2.5) size. This part of our argument is inspired by a well-known greedy approximation algorithm for the weighted set-cover problem.
AB - We show an Ω(e n2.5) lower bound for general depth four arithmetic circuits computing an explicit n-variate degree-Θ(n) multilinear polynomial over any field of characteristic zero. To our knowledge, and as stated in the survey [88], no super-quadratic lower bound was known for depth four circuits over fields of characteristic 6= 2 before this work. The previous best lower bound is Ω(e n1.5) [85], which is a slight quantitative improvement over the roughly Ω(n1.33) bound obtained by invoking the super-linear lower bound for constant depth circuits in [73,86]. Our lower bound proof follows the approach of the almost cubic lower bound for depth three circuits in [53] by replacing the shifted partials measure with a suitable variant of the projected shifted partials measure, but it differs from [53]'s proof at a crucial step - namely, the way “heavy” product gates are handled. Loosely speaking, a heavy product gate has a relatively high fan-in. Product gates of a depth three circuit compute products of affine forms, and so, it is easy to prune Θ(n) many heavy product gates by projecting the circuit to a low-dimensional affine subspace [53,87]. However, in a depth four circuit, the second (from the top) layer of product gates compute products of polynomials having arbitrary degree, and hence it was not clear how to prune such heavy product gates from the circuit. We show that heavy product gates can also be eliminated from a depth four circuit by projecting the circuit to a low-dimensional affine subspace, unless the heavy gates together account for Ω(e n2.5) size. This part of our argument is inspired by a well-known greedy approximation algorithm for the weighted set-cover problem.
KW - Depth four arithmetic circuits
KW - Projected Shifted Partials
KW - Super-quadratic lower bound
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U2 - 10.4230/LIPIcs.CCC.2020.23
DO - 10.4230/LIPIcs.CCC.2020.23
M3 - Conference contribution
AN - SCOPUS:85089368938
T3 - Leibniz International Proceedings in Informatics, LIPIcs
BT - 35th Computational Complexity Conference, CCC 2020
A2 - Saraf, Shubhangi
PB - Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing
T2 - 35th Computational Complexity Conference, CCC 2020
Y2 - 28 July 2020 through 31 July 2020
ER -