A Synchronous-Sampling Impedance-Readout IC with Baseline-Cancellation-Based Two-Step Conversion for Fast Neural Electrical Impedance Tomography

Electrical impedance tomography (EIT) is widely used for functional imaging of the bio-impedance of body parts for various applications, such as lung ventilation monitoring [1]. It was recently shown that 'fast neural EIT' with far enhanced temporal resolution (frame rate) can provide the neural activity monitoring and functional localization of the active peripheral nerve at the same time [2]. In an EIT system, to reconstruct an impedance tomography image (Fig. 1(a)), an AC current is injected from a current generator (ICG) into the target bioimpedance network ZBIO through an electrode pair (channel) in a rotational manner, while demodulating the voltages appeared at all the other channels. The I/Q demodulation is the most popular way to extract the resistance and reactance information of ZBIO [1]. For the neural EIT, however, this method cannot support a high enough frame rate, failing to acquire neural activities, mainly due to the downconversion to DC and low-pass filtering. As shown in Fig. 1(a), many cycles of the AC input signal are needed for the I and Q outputs to be well settled to their final values. A higher excitation frequency (fCG) can be used for faster settling in conventional applications, but in the neural EIT, fCG should be <20kHz for high SNR image acquisition [2]. Alternatively, peak detection can be used [3], but it needs a much faster sampling clock than fCG, consuming a large dynamic power in all the demodulation channels.