Adaptive Reduction of the Frequency Search Space for Multi- V_dd Digital Circuits Using Variation Sensitive Ring Oscillators

Increasing process variations, coupled with the need for highly adaptable circuits, bring about tough new challenges regarding circuit testing. Circuit adaptation for process and workload variability require costly characterization/test cycles for each chip, to extract particular V_dd/f_max behavior of the device under test (DUT). Consequently, the test cost associated with frequency binning and the f_max search is significant. This cost is further increased for chips that support dynamic voltage scaling, necessitating the calibration of f_max at multiple V_dd levels. In order to reduce this burden, we propose an adaptive statistical technique to reduce the f_max search space across multiple V_dd levels by reusing the information previously obtained from the DUT during test-time. The proposed solution employs statistical relations between the speed of the ring oscillators sensitive to different process parameters and speed of the DUT as well as the correlation between the DUT speeds at multiple V_dd levels in improving the prediction of the DUT's fmax. The proposed adaptive solution reduces the test/characterization time and cost at no area or test overhead; such an approach is being explored for the first time to the best of our knowledge. Experiments on a set of ISCAS benchmarks show up to 8x improvement in adaptively reducing the search space for f_max at multiple V_dd levels.