Adroit use of dark silicon for power, performance and reliability optimisation of NoCs

Haseeb Bokhari, Muhammad Shafique, Jörg Henkel, Sri Parameswaran

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract

Continuous transistor scaling has enabled designers to integrate increasing numbers of cores on a chip. Packet-switched Network-on-Chip (NoC) is envisioned as a scalable and cost effective communication fabric for multi-core architectures with tens and hundreds of cores. The failure of Dennard’s scaling has resulted in a situation where we have abundant transistors, but not enough power to switch on these transistors simultaneously, a phenomenon aptly named dark silicon. Previous research on dark silicon proposed integrating application-specific accelerators or cores to improve energy efficiency and reliability, neglecting the interplay of dark silicon and NoC architectures. This chapter proposes two NoC architectures that exploit dark silicon to improve the energy efficiency, performance and reliability of the on-chip interconnect. The first proposal is an on-chip interconnect, named darkNoC, that consists of multiple NoCs where each NoC is optimised at design time using multi-vt optimisation for different voltage-frequency (VF) levels. This architecture is based on the observation that instead of applying Dynamic Voltage and Frequency Scaling (DVFS) to a router that has been designed to operate at a higher VF level, using a router that has been designed specifically for a lower VF level is more energy efficient. The second proposal is SuperNet NoC architecture, that exchanges dark silicon for optimising the energy, performance and reliability of on-chip interconnect. SuperNet consists of two parallel NoC planes that are optimised for different VF levels, and can be configured at runtime to operate in energy efficient mode, performance mode or reliability mode. The reliability mode provides safety against soft error in the data path and control path.

Original languageEnglish (US)
Title of host publicationThe Dark Side of Silicon
Subtitle of host publicationEnergy Efficient Computing in the Dark Silicon Era
PublisherSpringer International Publishing
Pages291-325
Number of pages35
ISBN (Electronic)9783319315966
ISBN (Print)9783319315942
DOIs
StatePublished - Jan 1 2017

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

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