Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Satwik Patnaik, Nikhil Rangarajan, Johann Knechtel, Ozgur Sinanoglu, Shaloo Rakheja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

Original languageEnglish (US)
Title of host publicationProceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages97-102
Number of pages6
Volume2018-January
ISBN (Electronic)9783981926316
DOIs
StatePublished - Apr 19 2018
Event2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 - Dresden, Germany
Duration: Mar 19 2018Mar 23 2018

Other

Other2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
CountryGermany
CityDresden
Period3/19/183/23/18

Fingerprint

Hall effect devices
Spin Hall effect
Intellectual property
Switches
Boolean functions
Networks (circuits)
Polymorphism
Cryptography
Monitoring
Hardware security
Attack

ASJC Scopus subject areas

  • Safety, Risk, Reliability and Quality
  • Hardware and Architecture
  • Software
  • Information Systems and Management

Cite this

Patnaik, S., Rangarajan, N., Knechtel, J., Sinanoglu, O., & Rakheja, S. (2018). Advancing hardware security using polymorphic and stochastic spin-hall effect devices. In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 (Vol. 2018-January, pp. 97-102). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE.2018.8341986

Advancing hardware security using polymorphic and stochastic spin-hall effect devices. / Patnaik, Satwik; Rangarajan, Nikhil; Knechtel, Johann; Sinanoglu, Ozgur; Rakheja, Shaloo.

Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. p. 97-102.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Patnaik, S, Rangarajan, N, Knechtel, J, Sinanoglu, O & Rakheja, S 2018, Advancing hardware security using polymorphic and stochastic spin-hall effect devices. in Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 97-102, 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018, Dresden, Germany, 3/19/18. https://doi.org/10.23919/DATE.2018.8341986
Patnaik S, Rangarajan N, Knechtel J, Sinanoglu O, Rakheja S. Advancing hardware security using polymorphic and stochastic spin-hall effect devices. In Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January. Institute of Electrical and Electronics Engineers Inc. 2018. p. 97-102 https://doi.org/10.23919/DATE.2018.8341986
Patnaik, Satwik ; Rangarajan, Nikhil ; Knechtel, Johann ; Sinanoglu, Ozgur ; Rakheja, Shaloo. / Advancing hardware security using polymorphic and stochastic spin-hall effect devices. Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers Inc., 2018. pp. 97-102
@inproceedings{fd98ca8ac6854b4db5c2f3f879c2b0f8,
title = "Advancing hardware security using polymorphic and stochastic spin-hall effect devices",
abstract = "Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.",
author = "Satwik Patnaik and Nikhil Rangarajan and Johann Knechtel and Ozgur Sinanoglu and Shaloo Rakheja",
year = "2018",
month = "4",
day = "19",
doi = "10.23919/DATE.2018.8341986",
language = "English (US)",
volume = "2018-January",
pages = "97--102",
booktitle = "Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Advancing hardware security using polymorphic and stochastic spin-hall effect devices

AU - Patnaik, Satwik

AU - Rangarajan, Nikhil

AU - Knechtel, Johann

AU - Sinanoglu, Ozgur

AU - Rakheja, Shaloo

PY - 2018/4/19

Y1 - 2018/4/19

N2 - Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

AB - Protecting intellectual property (IP) in electronic circuits has become a serious challenge in recent years. Logic locking/encryption and layout camouflaging are two prominent techniques for IP protection. Most existing approaches, however, particularly those focused on CMOS integration, incur excessive design overheads resulting from their need for additional circuit structures or device-level modifications. This work leverages the innate polymorphism of an emerging spin-based device, called the giant spin-Hall effect (GSHE) switch, to simultaneously enable locking and camouflaging within a single instance. Using the GSHE switch, we propose a powerful primitive that enables cloaking all the 16 Boolean functions possible for two inputs. We conduct a comprehensive study using state-of-the-art Boolean satisfiability (SAT) attacks to demonstrate the superior resilience of the proposed primitive in comparison to several others in the literature. While we tailor the primitive for deterministic computation, it can readily support stochastic computation; we argue that stochastic behavior can break most, if not all, existing SAT attacks. Finally, we discuss the resilience of the primitive against various side-channel attacks as well as invasive monitoring at runtime, which are arguably even more concerning threats than SAT attacks.

UR - http://www.scopus.com/inward/record.url?scp=85048812071&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048812071&partnerID=8YFLogxK

U2 - 10.23919/DATE.2018.8341986

DO - 10.23919/DATE.2018.8341986

M3 - Conference contribution

VL - 2018-January

SP - 97

EP - 102

BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -