AES design space exploration new line for scan attack resiliency

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Crypto-chips are vulnerable to side-channel attacks. Scan attack is one such side-channel attack which uses the scan-based DFT test infrastructure to leak the secret information of the crypto-chip. In the presence of scan, an attacker can run the chip in normal mode, and then by switching to the test mode, retrieve the intermediate results of the crypto-chip. Using only a few input-output pairs one can retrieve the entire secret key. Almost all the scan attacks on AES crypto-chip use the same iterative 128-bit AES design where the round register is placed exactly after the round operation. However, the attack potency may vary depending on the design of AES. In this work, we consider various designs of AES. We shed light on the impact of design style on the scan attack. We also consider response compaction in our analysis. We show that certain design decisions deliver inherent resistance to scan attack.

Original languageEnglish (US)
Title of host publication2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
EditorsLorena Garcia
PublisherIEEE Computer Society
EditionJanuary
ISBN (Electronic)9781479960163
DOIs
StatePublished - Jan 7 2015
Event2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico
Duration: Oct 6 2014Oct 8 2014

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
NumberJanuary
Volume2015-January
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Other

Other2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
CountryMexico
CityPlaya del Carmen
Period10/6/1410/8/14

Keywords

  • AES Scan Chain
  • Scan Attack
  • Scan-based DFT
  • Security
  • Testability

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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  • Cite this

    Ali, S. S., Sinanoglu, O., & Karri, R. (2015). AES design space exploration new line for scan attack resiliency. In L. Garcia (Ed.), 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings (January ed.). [7004193] (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-January, No. January). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2014.7004193