AES design space exploration new line for scan attack resiliency

Sk Subidh Ali; Ozgur Sinanoglu; Ramesh Karri

doi:10.1109/VLSI-SoC.2014.7004193

AES design space exploration new line for scan attack resiliency

Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Crypto-chips are vulnerable to side-channel attacks. Scan attack is one such side-channel attack which uses the scan-based DFT test infrastructure to leak the secret information of the crypto-chip. In the presence of scan, an attacker can run the chip in normal mode, and then by switching to the test mode, retrieve the intermediate results of the crypto-chip. Using only a few input-output pairs one can retrieve the entire secret key. Almost all the scan attacks on AES crypto-chip use the same iterative 128-bit AES design where the round register is placed exactly after the round operation. However, the attack potency may vary depending on the design of AES. In this work, we consider various designs of AES. We shed light on the impact of design style on the scan attack. We also consider response compaction in our analysis. We show that certain design decisions deliver inherent resistance to scan attack.

Original language	English (US)
Title of host publication	2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
Editors	Lorena Garcia
Publisher	IEEE Computer Society
Edition	January
ISBN (Electronic)	9781479960163
DOIs	https://doi.org/10.1109/VLSI-SoC.2014.7004193
State	Published - Jan 7 2015
Event	2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico Duration: Oct 6 2014 → Oct 8 2014

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Number	January
Volume	2015-January
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Other

Other	2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
Country/Territory	Mexico
City	Playa del Carmen
Period	10/6/14 → 10/8/14

Keywords

AES Scan Chain
Scan Attack
Scan-based DFT
Security
Testability

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-SoC.2014.7004193

Cite this

Ali, S. S., Sinanoglu, O., & Karri, R. (2015). AES design space exploration new line for scan attack resiliency. In L. Garcia (Ed.), 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings (January ed.). Article 7004193 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-January, No. January). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2014.7004193

AES design space exploration new line for scan attack resiliency. / Ali, Sk Subidh; Sinanoglu, Ozgur ; Karri, Ramesh.
2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings. ed. / Lorena Garcia. January. ed. IEEE Computer Society, 2015. 7004193 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2015-January, No. January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ali, SS, Sinanoglu, O & Karri, R 2015, AES design space exploration new line for scan attack resiliency. in L Garcia (ed.), 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings. January edn, 7004193, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, no. January, vol. 2015-January, IEEE Computer Society, 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, 10/6/14. https://doi.org/10.1109/VLSI-SoC.2014.7004193

Ali SS, Sinanoglu O , Karri R. AES design space exploration new line for scan attack resiliency. In Garcia L, editor, 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings. January ed. IEEE Computer Society. 2015. 7004193. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; January). doi: 10.1109/VLSI-SoC.2014.7004193

Ali, Sk Subidh ; Sinanoglu, Ozgur ; Karri, Ramesh. / AES design space exploration new line for scan attack resiliency. 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings. editor / Lorena Garcia. January. ed. IEEE Computer Society, 2015. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; January).

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AES design space exploration new line for scan attack resiliency

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Keywords

ASJC Scopus subject areas

Access to Document

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