Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Yakun Sophia Shao, Brandon Reagen, Gu Yeon Wei, David Brooks

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.

Original languageEnglish (US)
Title of host publication41st Annual International Symposium on Computer Architecture, ISCA 2014 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages97-108
Number of pages12
ISBN (Print)9781479943968
DOIs
StatePublished - 2014
Event2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014 - Minneapolis, MN, United States
Duration: Jun 14 2014Jun 18 2014

Publication series

NameProceedings - International Symposium on Computer Architecture
ISSN (Print)1063-6897

Conference

Conference2014 ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014
CountryUnited States
CityMinneapolis, MN
Period6/14/146/18/14

ASJC Scopus subject areas

  • Hardware and Architecture

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