Algorithm level re-computing - A register transfer level concurrent error detection technique

K. Wu, R. Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Complier (BC) to implement the technique.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages537-543
Number of pages7
StatePublished - 2001
EventInternational Conference on Computer-Aided Design 2001 - San Jose, CA, United States
Duration: Nov 4 2001Nov 8 2001

Other

OtherInternational Conference on Computer-Aided Design 2001
CountryUnited States
CitySan Jose, CA
Period11/4/0111/8/01

ASJC Scopus subject areas

  • Software

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