TY - JOUR
T1 - Algorithm level re-computing using implementation diversity
T2 - A register transfer level concurrent error detection technique
AU - Karri, Ramesh
AU - Wu, Kaijie
N1 - Funding Information:
Manuscript received May 7, 2001; revised June 15, 2002. This work was supported by NSF CAREER Award CCR 996139. The authors are with the Electrical and Computer Engineering Department, Polytechnic University, Brooklyn, NY 11201 USA (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TVLSI.2002.808440
PY - 2002/12
Y1 - 2002/12
N2 - Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.
AB - Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the synopsys behavior complier (BC), to validate the schemes.
KW - Concurrent error detection
KW - Fault-tolerance
KW - Reliability
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U2 - 10.1109/TVLSI.2002.808440
DO - 10.1109/TVLSI.2002.808440
M3 - Article
AN - SCOPUS:0037002343
SN - 1063-8210
VL - 10
SP - 864
EP - 875
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 6
ER -