Algorithm level re-computing with allocation diversity: A register transfer level time redundancy based concurrent error detection technique

Kaijie Wu, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.

Original languageEnglish (US)
Title of host publicationIEEE International Test Conference (TC)
Pages221-229
Number of pages9
StatePublished - 2001
EventInternational Test Conference 2001 Proceedings - Baltimore, MD, United States
Duration: Oct 30 2001 → Nov 1 2001

Other

OtherInternational Test Conference 2001 Proceedings
CountryUnited States
CityBaltimore, MD
Period10/30/01 → 11/1/01

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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