Algorithm level re-computing with allocation diversity: A register transfer level time redundancy based concurrent error detection technique

Kaijie Wu; Ramesh Karri

Algorithm level re-computing with allocation diversity: A register transfer level time redundancy based concurrent error detection technique

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.

Original language	English (US)
Title of host publication	IEEE International Test Conference (TC)
Pages	221-229
Number of pages	9
State	Published - 2001
Event	International Test Conference 2001 Proceedings - Baltimore, MD, United States Duration: Oct 30 2001 → Nov 1 2001

Other

Other	International Test Conference 2001 Proceedings
Country	United States
City	Baltimore, MD
Period	10/30/01 → 11/1/01

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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title = "Algorithm level re-computing with allocation diversity: A register transfer level time redundancy based concurrent error detection technique",

abstract = "In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.",

author = "Kaijie Wu and Ramesh Karri",

year = "2001",

language = "English (US)",

pages = "221--229",

booktitle = "IEEE International Test Conference (TC)",

note = "International Test Conference 2001 Proceedings ; Conference date: 30-10-2001 Through 01-11-2001",

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T2 - International Test Conference 2001 Proceedings

AU - Wu, Kaijie

AU - Karri, Ramesh

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N2 - In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.

AB - In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.

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M3 - Conference contribution

AN - SCOPUS:0035680769

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EP - 229

BT - IEEE International Test Conference (TC)

Y2 - 30 October 2001 through 1 November 2001

ER -

Algorithm level re-computing with allocation diversity: A register transfer level time redundancy based concurrent error detection technique

Abstract

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ASJC Scopus subject areas

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