Abstract
In this paper we propose an algorithm-level time redundancy based CED scheme that exploits the hardware allocation diversity at the Register Transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the re-computation. We show that proposed scheme provides very good CED capability with very low area overhead.
Original language | English (US) |
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Title of host publication | IEEE International Test Conference (TC) |
Pages | 221-229 |
Number of pages | 9 |
State | Published - 2001 |
Event | International Test Conference 2001 Proceedings - Baltimore, MD, United States Duration: Oct 30 2001 → Nov 1 2001 |
Other
Other | International Test Conference 2001 Proceedings |
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Country/Territory | United States |
City | Baltimore, MD |
Period | 10/30/01 → 11/1/01 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials