Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection

Kaijie Wu, Ramesh Karri

Research output: Contribution to journalArticle

Abstract

In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.

Original languageEnglish (US)
Pages (from-to)1077-1087
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume21
Issue number9
DOIs
StatePublished - Sep 2002

Keywords

  • Algorithm level recomputing
  • Concurrent error detection
  • Fault tolerance
  • High-level synthesis
  • Register transfer level

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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