Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection

Kaijie Wu; Ramesh Karri

doi:10.1109/TCAD.2002.801110

Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.

Original language	English (US)
Pages (from-to)	1077-1087
Number of pages	11
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	21
Issue number	9
DOIs	https://doi.org/10.1109/TCAD.2002.801110
State	Published - Sep 2002

Keywords

Algorithm level recomputing
Concurrent error detection
Fault tolerance
High-level synthesis
Register transfer level

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2002.801110

Cite this

@article{27adcfbbf928494a93f6264f7b010c7f,

title = "Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection",

abstract = "In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.",

keywords = "Algorithm level recomputing, Concurrent error detection, Fault tolerance, High-level synthesis, Register transfer level",

author = "Kaijie Wu and Ramesh Karri",

note = "Funding Information: Manuscript received July 30, 2001. This work was supported in part by the National Science Foundation under CAREER Award CCR 996139. This paper was recommended by Associate Editor R. Camposano. The authors are with the Department of Electrical and Computer Engineering, Polytechnic University, Brooklyn, NY 11201 USA (e-mail: kaijie@ photon.poly.edu; [email protected]). Publisher Item Identifier 10.1109/TCAD.2002.801110.",

year = "2002",

month = sep,

doi = "10.1109/TCAD.2002.801110",

language = "English (US)",

volume = "21",

pages = "1077--1087",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Algorithm level recomputing using allocation diversity

T2 - A register transfer level approach to time redundancy-based concurrent error detection

AU - Wu, Kaijie

AU - Karri, Ramesh

N1 - Funding Information: Manuscript received July 30, 2001. This work was supported in part by the National Science Foundation under CAREER Award CCR 996139. This paper was recommended by Associate Editor R. Camposano. The authors are with the Department of Electrical and Computer Engineering, Polytechnic University, Brooklyn, NY 11201 USA (e-mail: kaijie@ photon.poly.edu; [email protected]). Publisher Item Identifier 10.1109/TCAD.2002.801110.

PY - 2002/9

Y1 - 2002/9

N2 - In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.

AB - In this paper, the authors propose an algorithm-level time redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.

KW - Algorithm level recomputing

KW - Concurrent error detection

KW - Fault tolerance

KW - High-level synthesis

KW - Register transfer level

UR - http://www.scopus.com/inward/record.url?scp=0036733232&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036733232&partnerID=8YFLogxK

U2 - 10.1109/TCAD.2002.801110

DO - 10.1109/TCAD.2002.801110

M3 - Article

AN - SCOPUS:0036733232

SN - 0278-0070

VL - 21

SP - 1077

EP - 1087

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 9

ER -

Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection

Abstract

Keywords

ASJC Scopus subject areas

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