Algorithm-level recomputing with shifted operands: Register transfer concurrent error detection technique

Research output: Contribution to journal › Article › peer-review

Original language	English (US)
Pages (from-to)	413-422
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	25
Issue number	3
State	Published - Mar 2006

Cite this

@article{a50dc60651674ed88a0b8a678262c63b,

title = "Algorithm-level recomputing with shifted operands: Register transfer concurrent error detection technique",

author = "K Wu and Ramesh Karri",

year = "2006",

month = mar,

language = "English (US)",

volume = "25",

pages = "413--422",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Algorithm-level recomputing with shifted operands

T2 - Register transfer concurrent error detection technique

AU - Wu, K

AU - Karri, Ramesh

PY - 2006/3

Y1 - 2006/3

M3 - Article

SN - 0278-0070

VL - 25

SP - 413

EP - 422

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 3

ER -