TY - GEN
T1 - ALICE
T2 - 59th ACM/IEEE Design Automation Conference, DAC 2022
AU - Tomajoli, Chiara Muscari
AU - Collini, Luca
AU - Bhandari, Jitendra
AU - Moosa, Abdul Khader Thalakkattu
AU - Tan, Benjamin
AU - Tang, Xifan
AU - Gaillardon, Pierre Emmanuel
AU - Karri, Ramesh
AU - Pilato, Christian
N1 - Funding Information:
R. Karri was supported in part by ONR Award # N00014-18-1-2058, NSF Grant # 1526405, NYU Center for Cybersecurity, and NYUAD Center for Cybersecurity. X. Tang and P.-E. Gaillardon were supported in part by DARPA, under the grants # FA8650-18-2-7855 and # FA8650-18-2-7849.
Publisher Copyright:
© 2022 ACM.
PY - 2022/7/10
Y1 - 2022/7/10
N2 - Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design.
AB - Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers can rely on embedded reconfigurable devices to completely hide the real functionality of selected design portions unless the configuration string (bitstream) is provided. However, selecting such portions and creating the corresponding reconfigurable fabrics are still open problems. We propose ALICE, a design flow that addresses the EDA challenges of this problem. ALICE partitions the RTL modules between one or more reconfigurable fabrics and the rest of the circuit, automating the generation of the corresponding redacted design.
UR - http://www.scopus.com/inward/record.url?scp=85137530620&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85137530620&partnerID=8YFLogxK
U2 - 10.1145/3489517.3530543
DO - 10.1145/3489517.3530543
M3 - Conference contribution
AN - SCOPUS:85137530620
T3 - Proceedings - Design Automation Conference
SP - 781
EP - 786
BT - Proceedings of the 59th ACM/IEEE Design Automation Conference, DAC 2022
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 10 July 2022 through 14 July 2022
ER -