Various techniques can be used to reduce the test time and cost of chip development, some of which achieve their objective by reducing the test data volume through the implementation of compression technologies such as XOR-based decompressors. In the presence of XOR decompressor, the delivery of acceptable (encodable) test patterns might not be possible. The Align-Encode technique which manipulates the distribution of care bits in the test pattern could increase the delivery of more encodable test patterns. Yet a sequential algorithm, which computes the delay values for a test pattern given the XOR decompressor specifications, faces major drawbacks when applied on large test patterns. In this paper, we propose a parallel version of the Align-Encode algorithm which is designed to work on distributed memory architecture. It exploits the nature of the problem in order to make significant improvements in performance with respect to time as well as the number of encodable test patterns generated, and in test data compression as a result.
- Distributed processing
- Test data compression
- VLSI testing
ASJC Scopus subject areas
- Computer Networks and Communications