TY - JOUR
T1 - Align-encode delay assignment in the case of XOR-decompressors
T2 - Impact of parallel computations
AU - Almulla, Mohammed
AU - Sinanoglu, Ozgur
AU - Taha, Mohammed Nael
AU - Al-Awadhi, Nader
PY - 2009/12
Y1 - 2009/12
N2 - Various techniques can be used to reduce the test time and cost of chip development, some of which achieve their objective by reducing the test data volume through the implementation of compression technologies such as XOR-based decompressors. In the presence of XOR decompressor, the delivery of acceptable (encodable) test patterns might not be possible. The Align-Encode technique which manipulates the distribution of care bits in the test pattern could increase the delivery of more encodable test patterns. Yet a sequential algorithm, which computes the delay values for a test pattern given the XOR decompressor specifications, faces major drawbacks when applied on large test patterns. In this paper, we propose a parallel version of the Align-Encode algorithm which is designed to work on distributed memory architecture. It exploits the nature of the problem in order to make significant improvements in performance with respect to time as well as the number of encodable test patterns generated, and in test data compression as a result.
AB - Various techniques can be used to reduce the test time and cost of chip development, some of which achieve their objective by reducing the test data volume through the implementation of compression technologies such as XOR-based decompressors. In the presence of XOR decompressor, the delivery of acceptable (encodable) test patterns might not be possible. The Align-Encode technique which manipulates the distribution of care bits in the test pattern could increase the delivery of more encodable test patterns. Yet a sequential algorithm, which computes the delay values for a test pattern given the XOR decompressor specifications, faces major drawbacks when applied on large test patterns. In this paper, we propose a parallel version of the Align-Encode algorithm which is designed to work on distributed memory architecture. It exploits the nature of the problem in order to make significant improvements in performance with respect to time as well as the number of encodable test patterns generated, and in test data compression as a result.
KW - Align-Encode
KW - Distributed processing
KW - Test data compression
KW - VLSI testing
UR - http://www.scopus.com/inward/record.url?scp=77950342582&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77950342582&partnerID=8YFLogxK
U2 - 10.1142/S0219265909002571
DO - 10.1142/S0219265909002571
M3 - Article
AN - SCOPUS:77950342582
SN - 0219-2659
VL - 10
SP - 261
EP - 281
JO - Journal of Interconnection Networks
JF - Journal of Interconnection Networks
IS - 4
ER -