Abstract
In this paper, we present a mixed integer linear program (MIP) formulation for optimal allocation and binding in high level synthesis of VLSI circuits with on-chip fault-detection. Although fault detection can be achieved by simply duplicating the computation on disjoint hardware and voting on the result(s), such a strategy bears unnecessarily high hardware overhead. Alternately, we exploit fault-security - a novel algorithmic level, area-efficient, fault detection technique. This technique ameliorates the dedicated hardware required for the original and duplicate computations by imposing inter-copy hardware disjointness at a sub-computation level instead of at the overall computation level. Special constraints to ensure fault-security are explicitly incorporated during allocation and binding. Our experimental results show that fault-security can be implemented at much lower hardware overheads than straightforward duplication.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
Editors | Anon |
Publisher | IEEE |
Pages | 327-330 |
Number of pages | 4 |
State | Published - 1994 |
Event | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA Duration: Oct 10 1994 → Oct 12 1994 |
Other
Other | Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors |
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City | Cambridge, MA, USA |
Period | 10/10/94 → 10/12/94 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering