Allocation and binding during fault-secure microarchitecture analysis

In this paper, we present a mixed integer linear program (MIP) formulation for optimal allocation and binding in high level synthesis of VLSI circuits with on-chip fault-detection. Although fault detection can be achieved by simply duplicating the computation on disjoint hardware and voting on the result(s), such a strategy bears unnecessarily high hardware overhead. Alternately, we exploit fault-security - a novel algorithmic level, area-efficient, fault detection technique. This technique ameliorates the dedicated hardware required for the original and duplicate computations by imposing inter-copy hardware disjointness at a sub-computation level instead of at the overall computation level. Special constraints to ensure fault-security are explicitly incorporated during allocation and binding. Our experimental results show that fault-security can be implemented at much lower hardware overheads than straightforward duplication.