Allocation and binding during fault-secure microarchitecture analysis

Sergei Sokolov, Ramesh Karri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a mixed integer linear program (MIP) formulation for optimal allocation and binding in high level synthesis of VLSI circuits with on-chip fault-detection. Although fault detection can be achieved by simply duplicating the computation on disjoint hardware and voting on the result(s), such a strategy bears unnecessarily high hardware overhead. Alternately, we exploit fault-security - a novel algorithmic level, area-efficient, fault detection technique. This technique ameliorates the dedicated hardware required for the original and duplicate computations by imposing inter-copy hardware disjointness at a sub-computation level instead of at the overall computation level. Special constraints to ensure fault-security are explicitly incorporated during allocation and binding. Our experimental results show that fault-security can be implemented at much lower hardware overheads than straightforward duplication.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Editors Anon
PublisherIEEE
Pages327-330
Number of pages4
StatePublished - 1994
EventProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors - Cambridge, MA, USA
Duration: Oct 10 1994Oct 12 1994

Other

OtherProceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors
CityCambridge, MA, USA
Period10/10/9410/12/94

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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