TY - GEN
T1 - ALMOST
T2 - 60th ACM/IEEE Design Automation Conference, DAC 2023
AU - Chowdhury, Animesh B.
AU - Alrahis, Lilas
AU - Collini, Luca
AU - Knechtel, Johann
AU - Karri, Ramesh
AU - Garg, Siddharth
AU - Sinanoglu, Ozgur
AU - Tan, Benjamin
N1 - Funding Information:
This research was supported in part by NSF Award 1553419 and 2039607. The opinions, findings, and conclusions, or recommendations expressed are those of the author(s) and do not reflect the views of any sponsors.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where key-gate localities are vulnerable to learning. Thus, we call for security-aware logic synthesis. We propose ALMOST, a framework for adversarial learning to mitigate oracle-less ML attacks via synthesis tuning. ALMOST uses a simulated-annealing-based synthesis recipe generator, employing adversarially trained models that can predict state-of-the-art attacks' accuracies over wide ranges of recipes and key-gate localities. Experiments on ISCAS benchmarks confirm the attacks' accuracies drops to around 50% for ALMOST-synthesized circuits, all while not undermining design optimization.
AB - Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where key-gate localities are vulnerable to learning. Thus, we call for security-aware logic synthesis. We propose ALMOST, a framework for adversarial learning to mitigate oracle-less ML attacks via synthesis tuning. ALMOST uses a simulated-annealing-based synthesis recipe generator, employing adversarially trained models that can predict state-of-the-art attacks' accuracies over wide ranges of recipes and key-gate localities. Experiments on ISCAS benchmarks confirm the attacks' accuracies drops to around 50% for ALMOST-synthesized circuits, all while not undermining design optimization.
UR - http://www.scopus.com/inward/record.url?scp=85171620932&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85171620932&partnerID=8YFLogxK
U2 - 10.1109/DAC56929.2023.10247921
DO - 10.1109/DAC56929.2023.10247921
M3 - Conference contribution
AN - SCOPUS:85171620932
T3 - Proceedings - Design Automation Conference
BT - 2023 60th ACM/IEEE Design Automation Conference, DAC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 July 2023 through 13 July 2023
ER -