@inproceedings{97b8a9c727c34d14867801104580041a,
title = "An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC",
abstract = "We present an impedance-monitoring IC achieving a wide frequency range (FR) and fast output data rate (ODR). The proposed IC support a wide FR with improved spectral density by down-converting the signal to the intermediate frequency (fIF) in front of the instrumentation amplifier (IA) using the LO signal generated by a single-side-band (SSB) mixer. The proposed IF-sampling architecture does not require narrow-bandwidth (BW) low-pass filter (LPF), resulting in a fast ODR. A time-interleaved (TI) DFT is also employed to further improve the ODR. A band-pass delta-sigma ADC (BP-ΔΣ-ADC) with the auto-calibration and BP truncation is adopted to achieve the best noise performance at fIF. The fabricated IC achieves 0.35ΩRMS resolution in the FR from 4kHz to 8MHz with 122.1Hz BW while providing the ODR up to 31.25kS/s.",
author = "Kweon, {Soon Jae} and Joonho Gil and Chulhyun Park and Sein Oh and Yoontae Jung and Injun Choi and Cheon, {Song I.} and Dang, {Hung Phan} and Koo, {Ja Hyuck} and Geunhoe Kim and Sohmyung Ha and Minkyu Je",
note = "Funding Information: To support various real-time applications such as real-time NDFT can be adjusted from 28 to 214. This results in the proximity sensing, prosthesis hand control, and cancer minimum BW of 122.1Hz and the maximum ODR of diagnosis [1]–[4], impedance-monitoring ICs should offer a 31.25kS/s. Fig. 4(a) and (b) show the spectrums of two wide FR with sufficient spectral density and a fast ODR. The different types of LO signals. When XNOR gate is used for impedance-monitoring IC typically consists of a current down-converting to fIF, the odd-order harmonics of the CG{\textquoteright}s generator (CG) and a readout front-end (RX). When the CG output are also down-converted to fIF and causes distortion. injects a sinusoidal (or square or pseudo-sinusoidal) current When fDDS/fIN is small, our CG based on the DDS also has odd-into the impedance under test, the resulting voltage signal is order harmonics. However, as shown in Fig. 4(b), the modulated by the impedance. The RX then demodulates this harmonics caused by the CG are down-converted to integer voltage signal into real and imaginary parts of the impedance. multiples of fIF rather than fIF. As a result, the proposed IC One widely used RX architecture down-converts the supports FR up to 8MHz using a 32MHz system clock. modulated signal to DC after an IA [3]. This RX requires a Experimental results LPF with a very narrow BW to extract the DC output, limiting Fig. 5 shows measured results of the BP-ΔΣ-ADC when set the achievable ODR. Some other RXs that quantize the with 366.2Hz BW corresponding to 3 bins of 214-pt. DFT with modulated signal without down-conversion do not require a Hanning window. As shown in Fig. 5(a) and (b), 83.7-dB SNR narrow-BW LPF. However, they suffer from a limited FR due is achieved when fOSC = fIF. Fig. 5(c) shows SNR vs. input to the need for a high-speed ADC [4] and a wide-BW IA, amplitude. Fig. 6 shows the power spectrum of the LO signal. consuming a large power. Instead, an architecture using an fIF Harmonics of the LO signal generated by the SSB is much can be used (Fig. 1(a)) [5], [6]. Here the modulated voltage smaller than those generated by the XNOR. Figs. 7 and 8 show signal is down-converted to fIF in front of the IA, which the magnitude and phase of the time-varying impedance reduces the required ADC speed and IA BW. However, it also consisting of a 1-kohm resistor and 2 varactors when fIN = requires the narrow-BW LPF for attenuating unwanted 1MHz and ICG = 80µApp. The ODR can be controlled from harmonics caused by the two choppers and input square signal, 31.25kS/s/64 to 31.25kS/s. Fig. 9 shows the IC noise thus suffering from a low ODR. Moreover, this type of RX is performance when ICG = 80µApp with 1kΩ. 0.35ΩRMS is likely to have a poor spectral density because harmonics of the achieved when fIN = 8MHz and ODR = 0.5kS/s. The square signal can be down-converted to fIF by choppers. corresponding BW is 122.1Hz. Thanks to the TI DFT, the Proposed Impedance-Monitoring IC noise performance is improved when the ODR is fixed and a The block diagram of the proposed impedance-monitoring fast ODR is achieved for the same target noise performance. IC is shown in Fig. 1(b). It down-converts the modulated Fabricated in a 0.18-µm CMOS process, 2 channels occupy signal to fIF in front of the IA. To prevent that the harmonics 13.3mm2 including digital circuits (Fig. 10). Table I shows the of the CG{\textquoteright}s output are down-converted to fIF, a direct-digital performance summary compared with other state-of-the-arts. synthesizer (DDS) is employed in the CG, and a SSB mixer is Our IC achieves the wide FR and fast ODR compared to adopted in the RX, unlike [6] that uses a XNOR gate to others thanks to the IF BP sampling, TI DFT, and SSB mixer. generate fLO = fIN + fIF. After the down-conversion by the Due to the down-conversion in front of IA, our analog front-chopper and amplification by the IA, the BP-ΔΣ-ADC, which end consumes almost constant power even when fIN increases. is designed to have the minimum noise level at fIF, quantizes Acknowledgements: This work was supported by the Ministry of the signal at fIF without down-conversion to DC. Hence, we Trade, Industry and Energy, Korea under Grant 20000944. can avoid the use of the narrow-BW LPF and achieve a fast References ODR. Then, the DFT is performed to extract the complex [1] T. D.Nguyen etal., TIE, 68(3),2021.[2]Y.Yuetal., TBCAS, impedance value. A TI DFT is adopted to improve the ODR. 12(6), 2018. [3] J. Lee et al., CICC, 2020. [4] G. Qu et al., ISSCC, Fig. 2 shows the block diagram of the BP-ΔΣ-ADC. It has the 2016. [7]Y. Zhouetal., JSSC, 38(10), 2003.2018. [5] H. Ha, etal., SOVC, 2017. [6] H. Koet al., TCAS-II, 63(3), Publisher Copyright: {\textcopyright} 2021 JSAP.; 35th Symposium on VLSI Circuits, VLSI Circuits 2021 ; Conference date: 13-06-2021 Through 19-06-2021",
year = "2021",
month = jun,
day = "13",
doi = "10.23919/VLSICircuits52068.2021.9492406",
language = "English (US)",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 Symposium on VLSI Circuits, VLSI Circuits 2021",
}